ADF4150HV
Rev. 0 | Page 3 of 28
SPECIFICATIONS
AVDD = DVDD = SDVDD = 3.3 V ± 10%; VP = 6.0 V to 30 V; GND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating temperature
range is 40°C to +85°C.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFIN CHARACTERISTICS
Input Frequency
10
300
MHz
For f < 10 MHz, ensure slew rate > 21 V/μs
10
30
MHz
Reference doubler enabled (DB25 bit in
Register 2 is set to 1)
Input Sensitivity
0.7
AVDD
V p-p
Biased at AVDD/2; ac coupling ensures AVDD/2 bias
Input Capacitance
5.0
pF
Input Current
±60
μA
RF INPUT CHARACTERISTICS
For lower RFIN frequencies, ensure slew
rate > 400 V/μs
RF Input Frequency (RFIN)
0.5
3.0
GHz
10 dBm ≤ RF input power ≤ +5 dBm
Prescaler Output Frequency
750
MHz
PHASE DETECTOR
Phase Detector Frequency
26
MHz
Low noise mode
20
MHz
Low spur mode
26
MHz
Integer-N mode
HIGH VOLTAGE CHARGE PUMP
ICP Sink/Source
High Value
384
μA
RSET = 5.1 kΩ
Low Value
48
μA
RSET = 5.1 kΩ
RSET Range
3.3
10
kΩ
High Value vs. RSET
196
μA
RSET = 10 kΩ
594
μA
RSET = 3.3 kΩ
Sink and Source Current Matching
6
%
1.0 V ≤ VCP ≤ (VP 1.0 V); VP = 6 V to 30 V
Absolute ICP Accuracy
3
%
ICP vs. VCP
2.5
%
1.0 V ≤ VCP ≤ (VP 1.0 V)
ICP vs. Temperature
2.5
%
VCP = VP/2
ICP Leakage
2.5
nA
VCP = VP/2
LOGIC INPUTS
Input High Voltage, VINH
2.0
V
Input Low Voltage, VINL
0.6
V
Input Current, IINH/IINL
±1
μA
Input Capacitance, CIN
15.0
pF
LOGIC OUTPUTS
Output High Voltage, VOH
DVDD 0.4
V
CMOS output selected
Output High Current, IOH
500
μA
Output Low Voltage, VOL
0.4
V
IOL = 500 μA
POWER SUPPLIES
AVDD
3.0
3.6
V
DVDD, SDVDD
AVDD
V
VP
6.0
30
V
Set the VP supply at least 1 V above the
maximum desired tuning voltage
IP
1
2.5
mA
VP = 30 V
50
60
mA
6 to 24
mA
Each output divide-by-2 consumes 6 mA typ
20
32
mA
RF output stage is programmable
Low Power Sleep Mode
1
μA