參數(shù)資料
型號: EVAL-ADF4150HVEB1Z
廠商: Analog Devices Inc
文件頁數(shù): 7/28頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR ADF4150HV
標(biāo)準(zhǔn)包裝: 1
類型: 整數(shù) N 合成器(RF)
頻率: 3GHz
適用于相關(guān)產(chǎn)品: ADF4150HV
已供物品:
ADF4150HV
Rev. 0 | Page 15 of 28
RD2
REFERENCE
DOUBLER
0DISABLED
1ENABLED
RD1
REFERENCE DIVIDE-B Y-2
0
DISABLED
1
ENABLED
CP3
CP2
CP1
ICP (A)
5.1k
000
48
001
96
010
144
011
192
100
240
101
288
110
336
111
384
R10
R9
...
R2
R1
R COUNTER (R)
00
0
1
00
1
0
2
..
.
..
.
..
.
1
0
1020
1
0
1
1021
1
0
1022
1
1023
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DB1
DB0
0
L2
L1
M3
M2
M1
RD2
RD1
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
D1
0
CP3
CP2 CP1
U6
U5
1
U3
U2
U1 C3(0) C2(1) C1(0)
RD
IV
2
DBR
REFER
E
NC
E
DO
UB
L
E
R
D
B
R
CHARGE
PUMP
CURRENT
SETTING
10-BIT R COUNTER
DBR
CONTROL
BITS
LD
P
RE
S
E
R
V
E
D
P
O
W
E
R-
DO
W
N
C
P
T
HRE
E
-
ST
A
T
E
CO
UN
TER
RESET
LDF
MUXOUT
DO
UB
LE
BU
FFE
R
RESE
RVED
U5
LDP
010ns
16ns
RESERVED
BIT
0
RESERVED
1NORMAL
OPERATION
U3
POWER-DOWN
0DISABLED
1ENABLED
U2
CP
THREE-STATE
0DISABLED
1ENABLED
U1
COUNTER
RESET
0DISABLED
1ENABLED
D1
DOUBLE BUFFER
R4[DB22:DB20]
0DISABLED
1
ENABLED
U6
LDF
0FRAC-N
1INT-N
R
ESE
R
VED
M3
M2
M1
OUTPUT
0
THREE-STATE OUTPUT
00
1
DVDD
01
0
GND
0
1
R COUNTER OUTPUT
1
0
N DIVIDER OUTPUT
1
0
1
ANALOG LOCK DETECT
1
0
DIGITAL LOCK DETECT
1
RESERVED
L2
L1
NOISE MODE
00
LOW NOISE MODE
0
1
RESERVED
1
0
RESERVED
11
LOW SPUR MODE
LOW
NOISE AND
LOW SPUR
MODES
09
05
8-
01
8
DBR
Figure 22. Register 2 (R2)
C2
C1
CLOCK DIVIDER MODE
0
CLOCK DIVIDER OFF
0
1
RESERVED
1
0
RESYNC ENABLE
1
RESERVED
D12
D11
...
D2
D1
CLOCK DIVIDER VALUE
00
...
00
0
00
...
01
1
00
...
10
2
00
...
11
3
..
...
..
.
..
...
..
.
..
...
..
.
1
...
0
4092
1
...
0
1
4093
1
...
1
0
4094
1
...
1
4095
BO
O
S
T
E
N
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
DB2
DB1
DB0
0
B1
0
C2
C1
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
C3(0) C2(1) C1(1)
CONTROL
BITS
12-BIT CLOCK DIVIDER VALUE
CLK
DIV
MODE
RESE
RVED
B1
BOOST
ENABLE
0
DISABLED
1
ENABLED
RESERVED
0
00
09
05
8-
0
19
Figure 23. Register 3 (R3)
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