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參數(shù)資料
| 型號： | EVAL-ADF4158EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADF4158 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4158 |
| 主要屬性： | 單路分?jǐn)?shù)-N PLL |
| 已供物品： | 板 |
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Data Sheet
ADF4158
Rev. G | Page 3 of 36
REVISION HISTORY
3/14—Rev. F to Rev. G
Changes to Timeout Interval Section...........................................27
2/14—Rev. E to Rev. F
Changed CKJ to CLK, Table 3 .........................................................6
Changed VDD to VDD Parameter to DVDD to AVDD Parameter,
Table 4.................................................................................................7
Changes to 25-Bit Fixed Modulus Section...................................11
Changes to Figure 22 ......................................................................14
Added Σ-Δ Modulator Mode Section...........................................21
Changed 12-Bit Clock Divider Value Section to 12-Bit CLK2
Divider Value Section .....................................................................21
Changes to Clock Divider (DIV) Mode, 12-Bit CLK2 Divider
Value Section, and Figure 27..........................................................21
Changes to Frequency Deviation Section and Timeout Interval
Section ..............................................................................................27
Changes to FMCW Radar Ramp Settings Worked Example
Section ..............................................................................................28
Added External Control of Ramp Steps Section.........................30
Changes to Figure 42 ......................................................................30
Changes to Interrupt Modes and Frequency Readback
Section ..............................................................................................31
Added Fast Lock Mode Section.....................................................32
Changes to Fast Lock Timer and Register Sequences Section,
Fast Lock Example Section, and Fast Lock: Loop Filter Topology
Section ..............................................................................................32
3/13—Rev. D to Rev. E
Changes to Figure 7, Figure 8, Figure 9, and Figure 10................9
Changes to Figure 22 ......................................................................14
Changes to Negative Bleed Current Section, Readback to
MUXOUT Section, and Figure 27 ................................................21
Changes to Figure 28 ......................................................................22
Changes to FMCW Radar Ramp Settings Worked Example
Section ..............................................................................................27
6/12—Rev. C to Rev. D
Changes to Table 3 and Figure 3 .....................................................6
Added Figure 4; Renumbered Sequentially ...................................6
Added Negative Bleed Current Section........................................21
Changes to Figure 27 ......................................................................21
12/11—Rev. B to Rev. C
Changes to Features Section ............................................................1
Changes to Figure 6 Caption to Figure 9 Caption ........................9
Changes to Figure 11 ......................................................................10
Changes to Figure 19 ......................................................................12
Changes to Figure 20 ......................................................................13
Changed 12-Bit MOD Divider Section to 12-Bit CLK1 Divider
Section ..............................................................................................17
Changes to 12-Bit CLK1 Divider Section .....................................17
Changes to Figure 24 ......................................................................18
Changes to Delay Clock Select Section and Figure 29 ...............24
Changes to Timeout Interval Section...........................................27
Changes to FMCW Radar Ramp Settings Worked Example
Section ..............................................................................................28
Changes to Delayed Start, Example Section and Delay Between
Ramps, Example Section ................................................................29
Changes to Fast-Lock Timer and Register Sequences Section
and Fast Lock: An Example Section .............................................32
Changes to Ordering Guide...........................................................35
Added Automotive Products Section ...........................................35
9/11—Rev. A to Rev. B
Changes to Noise Characteristics Parameter.................................3
7/11—Rev. 0 to Rev. A
Changes to Figure 21 ......................................................................13
Changes to Figure 25 ......................................................................19
Changes to 12-Bit Clock Divider Value Section .........................20
Changes to Figure 28 ......................................................................22
Changes to FMCW Radar Ramp Settings Worked Example
Section ..............................................................................................26
Added Ramp Programming Sequence Section, and added
Other Waveforms Heading ............................................................27
Changes to Figure 36 ......................................................................28
Added Ramp Complete Signal to Muxout Section and changes
to Figure 40 ......................................................................................29
Added Figure 42; Renumbered Sequentially...............................30
Changes to Figure 45 ......................................................................31
Changes to Figure 46 ......................................................................33
4/10—Revision 0: Initial Version
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