參數(shù)資料
型號： EVAL-ADF4158EB1Z
廠商： Analog Devices Inc
文件頁數(shù)： 26/36頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADF4158
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，頻率合成器
嵌入式： 否
已用 IC / 零件： ADF4158
主要屬性： 單路分?jǐn)?shù)-N PLL
已供物品： 板
ADF4158
Data Sheet
Rev. G | Page 32 of 36
FAST LOCK MODE
The ADF4158 can operate in fast lock mode. In this mode, the
charge pump current is boosted and additional resistors are
connected to maintain the stability of the loop.
Fast Lock Timer and Register Sequences
When fast lock mode is enabled (Register R4, DB[20:19]), after
a write to Register R0, the PLL operates in a wide bandwidth
mode for a selected amount of time. Before fast lock is enabled,
the initialization sequence must be performed after the part is
first powered up (see the Initialization Sequence section). The
time in bandwidth mode is set by:
CLK1 × CLK2/fPFD = Time in Wide Bandwidth
where:
CLK1 = Register R2, DB[14:3].
CLK2 = Register R4, DB[18:7].
fPFD = the PFD frequency.
Note that the fast lock feature does not work in ramp mode.
Fast Lock Example
In this example, the PLL has fPFD of 100 MHz and requires being
in wide bandwidth mode for 12 μs.
CLK1 × CLK2/fPFD = 12 μs
CLK1 × CLK2 = (12 × 106)(100 × 106) = 1200
Therefore, CLK1 = 12 and CLK2 = 100, which results in 12 μs.
Fast Lock Loop Filter Topology
To use fast lock mode, an extra connection from the PLL to the
loop filter is needed. The damping resistor in the loop filter must
be reduced to of its value in wide bandwidth mode. This
reduction is required because the charge pump current is
increased by 16 in wide bandwidth mode, and stability must be
ensured.
To further enhance stability and mitigate frequency overshoot
during a frequency change in wide bandwidth mode, Resistor R3
is connected (see Figure 46). During fast lock, the SW1 pin is
shorted to ground, and the SW2 pin is connected to CP (set
Bits DB[20:19] in Register R4 to 01 for fast lock divider).
The following two topologies can be used:
Divide the damping resistor (R1) into two values (R1 and
R1A) that have a ratio of 1:3 (see Figure 46).
Connect an extra resistor (R1A) directly from SW1 (see
Figure 47). The extra resistor must be selected such that the
parallel combination of an extra resistor and the damping
resistor (R1) is reduced to of the original value of R1.
For both topologies, the ratio R3:R2 must equal 1:4.
VCO
CP
C1
C2
C3
R3
R2
R1
R1A
SW2
SW1
ADF4158
0
872
8-
0
32
Figure 46. Fast-Lock Loop Filter Topology—Topology 1
VCO
CP
C1
C2
C3
R3
R2
R1
R1A
SW2
SW1
ADF4158
0
872
8-
1
02
Figure 47. Fast-Lock Loop Filter Topology—Topology 2
For more fast lock topologies, see ADIsimPLL.
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