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參數(shù)資料
| 型號： | EVAL-ADF4158EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADF4158 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4158 |
| 主要屬性： | 單路分?jǐn)?shù)-N PLL |
| 已供物品： | 板 |
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Data Sheet
ADF4158
Rev. G | Page 17 of 36
R-DIVIDER REGISTER (R2) MAP
With Register R2 DB[2:0] set to [0, 1, 0], the on-chip R-divider
register is programmed as shown in Figure 25.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
CSR Enable
Setting this bit to 1 enables cycle slip reduction. This is a method
for improving lock times. Note that the signal at the PFD must
have a 50% duty cycle in order for cycle slip reduction to work.
In addition, the charge pump current setting must be set to a
minimum. See the Cycle Slip Reduction for Faster Lock Times
section for more information.
Also note that the cycle slip reduction feature can only be
operated when the phase detector polarity setting is positive
(DB6 in Register R3). It cannot be used if the phase detector
polarity is set to negative.
Charge Pump Current Setting
DB[27:24] set the charge pump current setting (see Figure 25).
Set these bits to the charge pump current that the loop filter is
designed with.
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the INT, FRAC,
and MOD counters, determines the overall division ratio from
the RFIN to the PFD input.
Operating at CML levels, it takes the clock from the RF input
stage and divides it down for the counters. It is based on a
synchronous 4/5 core. When set to 4/5, the maximum RF
frequency allowed is 3 GHz. Therefore, when operating the
ADF4158 above 3 GHz, the prescaler must be set to 8/9. The
prescaler limits the INT value.
With P = 4/5, NMIN = 23.
With P = 8/9, NMIN = 75.
RDIV2
Setting DB21 to 1 inserts a divide-by-2 toggle flip-flop between
the R-counter and the PFD. This can be used to provide a 50%
duty cycle signal at the PFD for use with cycle slip reduction.
Reference Doubler
Setting DB20 to 0 feeds the REFIN signal directly to the 5-bit RF
R-counter, disabling the doubler. Setting this bit to 1 multiplies
the REFIN frequency by a factor of 2 before feeding the signal
into the 5-bit R-counter. When the doubler is disabled, the REFIN
falling edge is the active edge at the PFD input to the fractional
synthesizer. When the doubler is enabled, both the rising edge
and falling edge of REFIN become active edges at the PFD input.
The maximum allowed REFIN frequency when the doubler is
enabled is 30 MHz.
5-Bit R-Counter
The 5-bit R-counter allows the input reference frequency (REFIN) to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 32 are allowed.
12-Bit CLK1 Divider
Bits DB[14:3] are used to program the CLK1 divider, which
determines the duration of the time step in ramp mode.
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