- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16855 > EVAL-ADF4158EB1Z (Analog Devices Inc)BOARD EVALUATION FOR ADF4158 PDF資料下載
參數(shù)資料
| 型號： | EVAL-ADF4158EB1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADF4158 |
| 標準包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4158 |
| 主要屬性： | 單路分數(shù)-N PLL |
| 已供物品： | 板 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
ADF4158
Data Sheet
Rev. G | Page 30 of 36
The following example explains how to set up and use this
function.
Example
fOUT = 5790 MHz
fDEV = 100 kHz
Number of steps = 50
Duration of a single step = 10 μs
Ramp mode must be either triangular (Register R3, DB[11:10]
= 01) or single ramp burst (Register R3, DB[11:10] = 11).
In the first case, the generated frequency range is calculated as
follows:
Δf = fDEV × (Number of Steps + 2) × (Number of Steps + 1)/2
= 132.6 MHz
In the second case, the generated frequency range is calculated
as follows:
Δf = fDEV × (Number of Steps + 1) × Number of Steps/2
= 127.5 MHz
The timer is set in the same way as for its linear ramps
described in the Waveform Generation section.
Activation of the parabolic ramp is achieved by setting Bit DB28
in Register R5 to 1.
Next the counter reset (DB3 in Register R3) should be set first
to 1 and then to 0.
Eventually, the ramp must be activated as described in the
Ramp Complete Signal to MUXOUT
Ramp complete signal on MUXOUT is shown in Figure 41.
08
728
-10
0
TIME
V
O
L
T
AG
E
F
RE
Q
UE
NC
Y
Figure 41. Ramp Complete Signal on MUXOUT
To activate this function DB[30:27] = 1111 in Register 0 and
DB[25:21] = 00011 in Register 4.
EXTERNAL CONTROL OF RAMP STEPS
The internal ramp clock can be bypassed and each step can be
triggered by a pulse on the TXDATA pin. This allows for more
transparent control of each step. Enable this feature by setting
Bit DB29 in Register R5 to 1.
F
RE
Q
UE
NC
Y
TIME
TXDATA
RFOUT
V
O
LTA
G
E
TIME
08
728
-14
8
Figure 42. External Control of Ramp Steps
Interrupt Modes and Frequency Readback
Interrupt modes are triggered from the rising edge of TXDATA.
Depending on the settings of DB[27:26] in Register R5, the
modes in Table 7 are activated.
Table 7. Interrupt Modes
Mode
Action
DB[27:26] = 00
Interrupt is off
DB[27:26] = 01
Interrupt on TXDATA, sweep continues
DB[27:26] = 11
Interrupt on TXDATA, sweep stops
When an interrupt takes place, the data consisting of the INT
and FRAC values can be read back via MUXOUT. The data is
made up of 37 bits, 12 of which represent the INT value and 25
the FRAC value.
The idea of frequency readback is shown in Figure 43.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RNF-100-1/8-BK-STK | HEATSHRINK RNF-100 1/8"X4' BLK |
| M3CCA-1418R | IDC CABLE - MKC14A/MC14M/MKC14A |
| M3AAA-1418R | IDC CABLE - MSC14A/MC14M/MSC14A |
| H1AXH-3036G | IDC CABLE - HSC30H/AE30G/X |
| A3AAH-1036G | IDC CABLE - ASC10H/AE10G/ASC10H |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADF4193EBZ1 | 功能描述:BOARD EVALUATION EB1 FOR ADF4193 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADF4193EBZ2 | 功能描述:BOARD EVALUATION EB2 FOR ADF4193 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADF4206-7EB1 | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR DUAL RF PLL FREQUENCY SYNTHESIZERS 制造商:Analog Devices 功能描述:DUAL RF PLL FREQ SYNTHESIZERS - Bulk |
| EVAL-ADF4208EB1 | 制造商:Analog Devices 功能描述:Evaluation Board For Dual RF PLL Frequency Synthesizers 制造商:Analog Devices 功能描述:DUAL RF PLL FREQ SYNTHESIZERS - Bulk |
| EVAL-ADF4212EB1 | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。