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參數(shù)資料
| 型號(hào)： | GE28F640W30B70 |
| 英文描述： | EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC |
| 中文描述： | 的EEPROM | FLASH動(dòng)畫| 4MX16 |的CMOS | BGA封裝| 56PIN |塑料 |
| 文件頁數(shù)： | 20/91頁 |
| 文件大小： | 994K |
| 代理商： | GE28F640W30B70 |
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1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
20
Datasheet
PBA = Partition Base Address. The very first address of a particular partition.
QA = Query code address.
WA = Word address of memory location to be written.
2. SRD = Status register data.
WD = Data to be written at location WA.
IC = Identifier code data.
PD = User programmable 4-word protection data.
QD = Query code data on D[7:0].
CD = Configuration register code data presented on device addresses A[15:0]. A[MAX:16] address bits can
select any partition
.
See
Table 13, “Configuration Register Definitions” on page 44
for configuration register
bits descriptions.
3. Commands other than those shown above are reserved by Intel for future device implementations and
should not be used.
3.3
Command Sequencing
When issuing a 2-cycle write sequence to the flash device, a read operation is allowed to occur
between
the two write cycles. The setup phase of a 2-cycle write sequence places the addressed
partition into read-status mode, so if the same partition is read before the second “confirm” write
cycle is issued, status register data will be returned. Reads from other partitions, however, can
return actual array data assuming the addressed partition is already in read-array mode.
Figure 2 on
page 20
and
Figure 3 on page 20
illustrate these two conditions.
By contrast, a write bus cycle may not interrupt a 2-cycle write sequence. Doing so causes a
command sequence error to appear in the status register.
Figure 4
illustrates a command sequence
error.
Figure 2. Normal Write and Read Cycles
Figure 3. Interleaving a 2-Cycle Write Sequence with an Array Read
Partition A
Partition A
Partition A
20h
D0h
FFh
Block Erase Setup
Block Erase Confirm
Read Array
Address [A]
WE# [W]
OE# [G]
Data [Q]
Partition B
Partition A
Partition B
Partition A
FFh
20h
Array Data
Bus Read
D0h
Read Array
Erase Setup
Erase Confirm
Address [A]
WE# [W]
OE# [G]
Data [Q]
相關(guān)PDF資料 |
PDF描述 |
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| GE28F640W30B85 | EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC |
| GE28F640W30T70 | EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC |
| GE28F640W30T85 | EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC |
| GF4435 | TRANSISTOR | MOSFET | P-CHANNEL | 30V V(BR)DSS | 8A I(D) | SO |
| GF4450 | TRANSISTOR | MOSFET | N-CHANNEL | 60V V(BR)DSS | 7.5A I(D) | SO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GE28F640W30B85 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC |
| GE28F640W30T70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC |
| GE28F640W30T85 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC |
| GE28F800B3BA90 | 制造商:Intel 功能描述:NOR Flash, 512K x 16, 45 Pin, Plastic, BGA |
| GE28F800B3TA90 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 Volt Advanced Boot Block Flash Memory |
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