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參數(shù)資料
| 型號： | GS8182T08GBD-167IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 2M X 8 DDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, ROHS COMPLIANT, FPBGA-165 |
| 文件頁數(shù)： | 13/37頁 |
| 文件大?。?/td> | 340K |
| 代理商： | GS8182T08GBD-167IT |
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Preliminary
GS8182T08/09/18/36BD-333/300/267/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00a 6/2007
20/37
2007, GSI Technology
AC Electrical Characteristics
Parameter
Symbol
-333
-300
-267
-250
-200
-167
Units
Notes
MinMax
Min
Max
MinMax
Clock
K, K Clock Cycle Time
C, C Clock Cycle Time
tKHKH
tCHCH
3.0
4.5
3.3
4.5
3.75
4.5
4.0
8.4
5.0
8.4
6.0
8.4
ns
tTKC Variable
tKCVar
—0.2
—
0.2
—0.2
ns
5
K, K Clock High Pulse Width
C, C Clock High Pulse Width
tKHKL
tCHCL
1.2
—
1.32
—
1.6
—
1.6
—
2.0
—
2.4
—
ns
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
tKLKH
tCLCH
1.2
—
1.32
—
1.6
—
1.6
—
2.0
—
2.4
—
ns
K to K High
C to C High
tKHKH
tCHCH
1.35
—
1.49
—
1.8
—
1.8
—
2.2
—
2.7
—
ns
K to K High
C to C High
tKHKH
tCHCH
1.35
—
1.49
—
1.8
—
1.8
—
2.2
—
2.7
—
ns
K, K Clock High to C, C Clock High
tKHCH
0
1.3
0
1.45
0
1.8
0
1.8
0
2.3
0
2.8
ns
DLL Lock Time
tKCLock
1024
—
1024
—
1024
—
1024
—
1024
—
1024
—
cycle
6
K Static to DLL reset
tKCReset
30
—
30
—
30
—
30
—
30
—
30
—
ns
Output Times
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
tKHQV
tCHQV
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
—
0.5
ns
3
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
tKHQX
tCHQX
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.5
—
ns
3
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
tKHCQV
tCHCQV
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
—
0.5
ns
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
tKHCQX
tCHCQX
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.5
—
ns
CQ, CQ High Output Valid
tCQHQV
—
0.25
—
0.27
—
0.30
—
0.30
—
0.35
—
0.40
ns
7
CQ, CQ High Output Hold
tCQHQX
–0.25
—
–0.27
—
–0.30
—
–0.30
—
–0.35
—
–0.40
—
ns
7
CQ Phase Distortion
tCQHCQH
1.10
—
1.24
—
1.55
—
1.55
—
1.95
—
2.45
—
ns
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
tKHQZ
tCHQZ
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
—
0.5
ns
3
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
tKHQX1
tCHQX1
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.5
—
ns
3
Setup Times
Address Input Setup Time
tAVKH
0.4
—
0.4
—
0.5
—
0.5
—
0.6
—
0.7
—
ns
Control Input Setup Time
tIVKH
0.4
—
0.4
—
0.5
—
0.5
—
0.6
—
0.7
—
ns
2
Data Input Setup Time
tDVKH
0.28
—
0.3
—
0.35
—
0.35
—
0.4
—
0.5
—
ns
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