參數(shù)資料
型號(hào)： GS8182T08GBD-167IT
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 2M X 8 DDR SRAM, 0.5 ns, PBGA165
封裝： 13 X 15 MM, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù)： 4/37頁(yè)
文件大?。?/td> 340K
代理商： GS8182T08GBD-167IT
Preliminary
GS8182T08/09/18/36BD-333/300/267/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00a 6/2007
12/37
2007, GSI Technology
Common I/O SigmaCIO DDR-II B2 SRAM Truth Table
B2 Byte Write Clock Truth Table
Kn
LD
R/W
DQ
Operation
A + 0
A + 1
↑
1
X
Hi-Z
Deselect
↑
00
D@Kn+1
Write
↑
01
Q@Kn+1
or
Cn+1
Q@Kn+2
or
Cn+2
Read
Note: Q is controlled by K clocks if C clocks are not used.
BW
Current Operation
D
K ↑
(tn+1)
K ↑
(tn+2)
K ↑
(tn)
K ↑
(tn+1)
K ↑
(tn+2)
TT
Write
Dx stored if BWn = 0 in both data transfers
D1
D2
TF
Write
Dx stored if BWn = 0 in 1st data transfer only
D1
X
FT
Write
Dx stored if BWn = 0 in 2nd data transfer only
XD2
FF
Write Abort
No Dx stored in either data transfer
XX
Notes:
1. “1” = input “high”; “0” = input “l(fā)ow”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
*Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles.
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