參數資料
型號： GT-48207
廠商： Galileo Technology Services, LLC
英文描述： Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級交換式 10+10/100 BaseX以太網控制器)
中文描述： 先進的交換式以太網控制器的10 10/100 BaseX（高級交換式10 10/100 BaseX以太網控制器）
文件頁數： 44/135頁
文件大小： 1619K
代理商： GT-48207
GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
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Revision 1.2
SerLinkStatus
I
Serial Link Status Indication: This pin is used to serially shift the Link Sta-
tus of ports 1 to 11 from the external PHY. LEDClk and LEDStb are used to
clock and strobe the data (assertion of LedStb indicates the beginning of the
link data stream). SerLinkStatus pin is sampled at the rising edge of LedClk.
It should be driven at the falling edge of the LEDClk.
Polarity:
High SerLinkStatus: link is good
Low SerLinkStatus: link fail.
LinkStatus[0]
I
Link Status Indication: This pin is used to indicate the Link Status of port 0
from the external PHY.
Polarity:
High LinkStatus[0]: link is good
Low LinkStatus[0]: link fail.
10/100Mbps Interface (MII)
TxEn[1:0]
O
Transmit Enable: Active HIGH. This output indicates that the packet is
being transmitted. TxEn is synchronous to TxClk.
TxClk[1:0]
I
Transmit Clock: Provides the timing reference for the transfer of TxEn, TxD
signals. TxClk frequency is one fourth of the data rate (25 MHz for 100Mbps,
2.5 MHz for 10Mbps, 60Mhz for 240Mbps). TxClk nominal frequency should
match the nominal frequency of RxClk for the same port.
TxD0[3:0]
O
Transmit Data 0: Outputs the Port0 Transmit Data. Synchronous to
TxClk[0].
TxD1[3:0]
O
Transmit Data 1: Outputs the Port1 Transmit Data. Synchronous to
TxClk[1].
Col[1:0]
I
Collision detect: Active HIGH. Indicates a collision has been detected on
the wire. This input is ignored in full-duplex mode. Col is not synchronous to
any clock.
RxD0[3:0]
I
Receive Data 0: Port 0 Receive Data. Synchronous to RxClk[0].
RxD1[3:0]
I
Receive Data 1: Port 1 Receive Data. Synchronous to RxClk[1].
RxEr[1:0]
I
Receive Error. Active HIGH. Indicates that an error was detected in the
received frame. This input is ignored when RxDV for the same port is inac-
tive.
RxClK[1:0]
I
Receive Clock. Provides the timing reference for the transfer of the
RxDV,RxD,RxEr signals (per port). Operates at either 25 MHz (100Mbps),
2.5 MHz (10Mbps) or 60Mhz (240Mbps). The nominal frequency of RxClk
(per port) should match the nominal frequency of that port’s TxClk.
RxDV[1:0]
I
Receive Data Valid: Active HIGH. Indicates that valid data is present on the
RxD lines. Synchronous to RxClk.
CrS[1:0]
I
Carrier Sense: Active HIGH. Indicates that either the transmit or receive
medium is non-idle. CrS is not synchronous to any clock.
Table 2:
Pin Functions (Continued)
Sy mbol
Ty pe
D e scr ipt io n
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