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參數(shù)資料
| 型號： | HSP43216JC-52Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC HALFBAND FILTER 84-PLCC |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 濾波器類型： | 半帶 |
| 濾波器數(shù)： | 4 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.21x29.21） |
| 包裝： | 管件 |
5
FN3365.10
October 6, 2008
For added flexibility, a spectrally reversed version of the
above process may be realized by configuring the Down
Convert processor to impart a positive fS/4 spectral shift on
the input signal. This has the effect of centering the lower
sideband of the input signal at DC and is achieved by
reversing the sign of the sine term in the quadrature mix as
shown below:
The direction of the spectral shift imparted by the Down
Convert Processor is set by the Upper Sideband/ Lower
Sideband control input, USB/LSB. When this input is high, a
-fS/4 spectral shift is used to center the input signal’s upper
sideband at DC. When asserted low, a spectral shift of fS/4
is used to center the lower sideband at DC. The SYNC
control input may be used to synchronize the incoming data
stream with the zero degree phase of the complex
exponential as described in the Operational Modes section.
The real and imaginary sample streams generated by the
down convert operation are passed to the Halfband Filter
block on the upper and lower processing legs respectively.
The Down Convert Processor is only active in Down Convert
and Decimate Mode, MODE1-0 = 10. In the other modes,
the data on the upper and lower processing legs pass
unaltered.
67-Tap Halfband Filter Processor
The processing required to implement the 67-Tap Halfband
filter is distributed across two polyphase branches
comprised of even and odd tap filters as shown in Figure 1.
The Even Tap Filter performs a filtering operation using the
even indexed coefficients (even phase) of the halfband filter.
The Odd Tap Filter uses the odd indexed coefficients (odd
phase) of the halfband filter. NOTE: the odd tap filter’s
processing reduces to a delay and scale operation since
the center tap is the only non-zero odd tap for a
halfband filter. Together the polyphase filters perform the
sum of-products required to implement the 67-tap halfband
filter in an architecture capable of supporting a variety of
operational modes. The frequency response of the halfband
filter is given graphically in Figure 2 and in tabular form in
Table 3. Table 2 shows the different modes and the related
frequency with which the spectra in Figure 2 is normalized.
The polyphase implementation of the halfband filter
provides the flexibility to realize a variety of filter
configurations. In Decimate by Two Mode, the outputs of
the each polyphase branch are summed to yield the filter
output. In Interpolate by Two mode, the polyphase filters
produce independent outputs which are multiplexed into a
single sample stream at the interpolated data rate. In the
Up Convert and Down Convert Modes, the polyphase
branches filter the real and imaginary components of a
complex sample stream with the equivalent of identical 67-
Tap Halfband Filters. For these modes, the real component
is processed by the Even Tap filter and the imaginary
component is processed by the Odd Tap filter. The
Operational Modes Section provides further details
regarding the data flow and operation of the Filter
Processor for the various modes.
As a standard DSP term, group delay is defined as the time
it takes to obtain valid filtered data given a certain input
pattern. Both the Even Tap and Odd Tap filters have an
identical group delay of 19 clocks relative to the operating
mode of the halfband. The group delay has been specified in
the data flow diagrams following this section. The delay
clocks equal CLK when INT/EXT = 0 and CLK/2 when
INT/EXT = 1.
NOTE: Pipeline delay specifies the time it takes for bits to
toggle at the output given a certain input pattern. The Odd tap
filter has a pipeline delay of 19 CLKs with respect to the
operating mode because it consists of only the center tap of the
67-tap halfband. The Even tap filter has a pipeline delay of 2-35
CLKs with respect to the operating mode.
TABLE 2. NORMALIZED FREQUENCY vs MODE
MODE
fS
Decimate by Two
CLK
Interpolate by Two
CLK/2
Down Convert and Decimate
CLK
Quadrature to Real
CLK/2
xn
()
ej πn2
()
x n
()
πn2
()
jx n
()
πn2
()
sin
+
cos
=
(EQ. 2)
0
-20
-40
-60
-80
-100
-120
0fS/4
FS/2
MAGNIT
UDE
(DB)
NORMALIZED FREQUENCY
3fS/8
fS/8
FIGURE 2. FREQUENCY RESPONSE OF 67-TAP HALFBAND
FILTER
HSP43216
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| HSP43216JI-52 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP43216VC-52 | 功能描述:有源濾波器 HALFBAND FILTER 100 PIN PQFP,COMM RoHS:否 制造商:Maxim Integrated 通道數(shù)量:1 截止頻率:150 KHz 電源電壓-最大:11 V 電源電壓-最小:4.74 V 最大工作溫度:+ 85 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP N 封裝:Tube |
| HSP43216VC-52Z | 功能描述:有源濾波器 W/ANNEAL HALFB & FILER 100 PIN PQFP RoHS:否 制造商:Maxim Integrated 通道數(shù)量:1 截止頻率:150 KHz 電源電壓-最大:11 V 電源電壓-最小:4.74 V 最大工作溫度:+ 85 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP N 封裝:Tube |
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