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參數(shù)資料
| 型號： | HSP43216JC-52Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 0K |
| 描述： | IC HALFBAND FILTER 84-PLCC |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 濾波器類型： | 半帶 |
| 濾波器數(shù)： | 4 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.21x29.21） |
| 包裝： | 管件 |
15
FN3365.10
October 6, 2008
As in the other modes, the operation of the HSP43216 in
Quadrature to real Conversion mode is analogous to that of
the polyphase solution described above. The data flow
diagrams for this particular mode are shown in Figures 21A
and 21B.
If Internal Multiplexing is specified (INT/EXT = 1), the real
and imaginary components of the quadrature input are fed
through AIN0-15 and BIN0-15 and processed on the upper
and lower legs respectively (see Figure 21A). Each
component of the complex input is interpolated, mixed with
the non-zero sine and cosine terms of the quadrature LO,
and multiplexed together into a real output sample stream
through AOUT0-15. Prior to the output multiplexer, the upper
and lower processing legs each run at the input data rate of
CLK/2 as indicated by the “” marking the various registers
and processing elements in Figure 21A. The complex input
sample stream may be synchronized with the zero degree
phase of the up converters quadrature LO by asserting the
SYNC control input one cycle prior to the targeted data
sample as shown in Figure 22. This ensures that the real
sample input on the upper processing leg will be mixed with
the zero degree cosine term. The minimum pipeline delay
through the real processing leg (upper leg) is 15 CLK’s and
the delay through the imaginary processing leg (lower leg) is
48 CLK’s.
If external multiplexing is selected (INT/EXT = 0), output
from the upper and lower processing legs exit through
AOUT0-15 and BOUT0-15 for multiplexing into a single data
stream off chip (see Figure 21B).This allows the processing
legs to run at the maximum CLK rate which coincides with
an interpolated output data rate of up to 104 MSPS.
NOTE: The output on BOUT0-15 precedes that on
AOUT0-15 in sample order. This requires a multiplexing
scenario which selects BOUT0-15 then AOUT0-15 on each
CLK of the HSP43216. With external multiplexing, the
minimum pipeline delay through the upper processing leg is
9 CLK’s and the pipeline delay through the lower processing
leg is 26 CLK’s as shown in Figure 21B. The SYNC control
input is used as described in the preceding paragraph.
Clock at Input data rate, CLK/2
FIGURE 21A. DATA FLOW DIAGRAM FOR QUADRATURE TO REAL CONVERSION MODE (INT/EXT = 1)
FIGURE 21B. DATA FLOW DIAGRAM FOR QUADRATURE TO REAL CONVERSION MODE (INT/EXT = 0)
EVEN TAP
FILTER
ODD TAP
FILTER
AIN0-15
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
1
2,-2,2,-2,...
BIN0-15
R
E
G
R
E
G
R
E
G
M
U
X
-2,2,-2,2,...
AOUT0-15
OEA
R
N
D
F
M
T
R
E
G
R
E
G
GROUP DELAY 19
PIPELINE DELAY 2-35
GROUP DELAY 19
PIPELINE DELAY 19
EVEN TAP
FILTER
ODD TAP
FILTER
AIN0-15
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
1
2,-2,2,-2,...
BIN0-15
R
E
G
R
E
G
-2,2,-2,2,...
AOUT0-15
OEA
R
N
D
F
M
T
R
E
G
R
E
G
BOUT0-15
OEB
R
N
D
F
M
T
R
E
G
R
E
G
GROUP DELAY 19
PIPELINE DELAY 2-32
GROUP DELAY 19
PIPELINE DELAY 19
0
CLK/2
SYNC
AIN0-15
FIGURE 22. DATA SYNCHRONIZATION WITH PROCESSING
LEGS (INT/EXT = 1)
BIN0-15
HSP43216
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP43216JI-52 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP43216VC-52 | 功能描述:有源濾波器 HALFBAND FILTER 100 PIN PQFP,COMM RoHS:否 制造商:Maxim Integrated 通道數(shù)量:1 截止頻率:150 KHz 電源電壓-最大:11 V 電源電壓-最小:4.74 V 最大工作溫度:+ 85 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP N 封裝:Tube |
| HSP43216VC-52Z | 功能描述:有源濾波器 W/ANNEAL HALFB & FILER 100 PIN PQFP RoHS:否 制造商:Maxim Integrated 通道數(shù)量:1 截止頻率:150 KHz 電源電壓-最大:11 V 電源電壓-最小:4.74 V 最大工作溫度:+ 85 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP N 封裝:Tube |
| HSP43220 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Decimating Digital Filter |
| HSP43220/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Decimating Digital Filter |
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