參數(shù)資料
型號: HY5PS12823F
英文描述: 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
中文描述: 64Mx8 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內存- 512M
文件頁數(shù): 59/66頁
文件大小: 862K
代理商: HY5PS12823F
Rev. 0.52/Nov. 02 59
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
AC OPERATING CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
V
IH(AC)
V
REF
+ 0.25
V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
V
IL(AC)
V
REF
- 0.25
V
Input Differential Voltage, CK and /CK inputs
V
ID(AC)
TBD
TBD
V
1
Input Crossing Point Voltage, CK and /CK inputs
V
IX(AC)
TBD
TBD
V
2
Parameter
Value
Unit
Reference Voltage
V
DDQ
x 0.5
V
Termination Voltage
V
DDQ
x 0.5
V
AC Input High Level Voltage (V
IH
, min)
V
REF
+ 0.25
V
AC Input Low Level Voltage (V
IL
, max)
V
REF
- 0.25
V
Input Timing Measurement Reference Level Voltage
V
REF
V
Output Timing Measurement Reference Level Voltage
V
TT
V
Input Signal maximum peak swing
1.5
V
Input minimum Signal Slew Rate
1
V/ns
Termination Resistor (R
T
)
TBD
Series Resistor (R
S
)
TBD
Output Load Capacitance for Access Time Measurement (C
L
)
TBD
pF
This Page will be changed by the standardization result of Jedec Committee.
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