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參數(shù)資料
| 型號： | HY5PS12823F |
| 英文描述： | 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M |
| 中文描述： | 64Mx8 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M |
| 文件頁數(shù)： | 7/66頁 |
| 文件大小： | 862K |
| 代理商： | HY5PS12823F |
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Rev. 0.52/Nov. 02 7
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK. Output
(read) data is referenced to the crossings of CK and CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are dis-
abled during SELF REFRESH. CKE is an SSTL_18 input, but will detect an LVCMOS LOW
level after Vdd is applied.
CS
Input
Chip Select : Enables or disables all inputs except CK, CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
A0 ~ A13
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
RAS, CAS, WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
ODT
Input
On Die Termination Control : ODT enables on die termination resistance internal to the
DDR II SDRAM. When enabled, on die termination is only applied to DQ, DQS, DQS,
RDQS, RDQS, and DM.
DM, RDQS
NC, RDQS
(LDM, UDM)
Input
Input Data Mask : DM is an input mask signal for write data. Input Data is masked when
DM is sampled High along with that input data during a WRITE access. DM is sampled on
both edges of DQS, Although DM pins are input only, the DM loading matches the DQ and
DQS loading. For the x16, LDM corresponds to the data on DQ0-7; UDM corresponds to
the data on DQ8-15.
Read Data Strobe for x8 Device : DM signal is muxed with RDQS. When read data strobe
option is enabled by EMRS, this muxed pin is used for read data strobe.
DQS, DQS
I/O
Differential Data Strobe Pair : Output with read data, input with write data. Edge aligned
with read data, centered in write data. Used to capture write data. Strobe options - Dif-
ferential or single ended is selected by EMRS. For the x16, LDQS corresponds to the data
on DQ0-7; UDQS corresponds to the data on DQ8-15.
DQ
I/O
Data input / output pin : Data bus
V
DD
/V
SS
Supply
Power supply for internal circuits and input buffers.
V
DDQ
/V
SSQ
Supply
Power supply for output buffers for noise immunity.
VDDL/VSSDL
Supply
Power supply for DLL circuits
V
REF
Supply
Reference voltage for inputs for SSTL interface.
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