參數(shù)資料
型號(hào)： HY5PS12823LF
英文描述： 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
中文描述： 64Mx8 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M
文件頁(yè)數(shù)： 28/66頁(yè)
文件大?。?/td> 862K
代理商： HY5PS12823LF
Rev. 0.52/Nov. 02 28
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
DLL ENABLE
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon return-
ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically
disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any
time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally
applied clock before an any command can be issued.
ADDITIVE LATENCY
Posted CAS, is a feature that allows a DRAM to latch CAS command immediately after the bank activate command (or
any time during the tRCD period) without tRCD delay. In side of DRAM, read or Write - CAS command is held for the
time of the Additive Latency (AL) before it is issued. Additive latency is programmed to EMRS and it determine internal
command hold time. Therefore, if read or write command are issued earlier than minimum tRCD delay, proper addtive
latency value must be chosen to insure and that value must be programmed to EMRS. In case of AL=0, operation is
the same with ormal SDRAM and DDR SDRAM.
DQS ENABLE
DDR-II SDRAM support both signle ended data strobe and differential data strobe. Differential Strobe is enabled by
issuing a Extended Mode Register Set command with bit A10 to set to zero. When differential data strobe is enabled,
timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. Differential Strobe is
disabled by issuing a Extended Mode Register Set command with bit A10 to set to one. In single ended data strobe
mode, timing relationships are measured relative to the rising or falling edges of DQS. It’s operation is the same with
DDR-I.
RDQS ENABLE
Read Data Strobe, feature is intended to simplify controller design when x4 configuration DRAM based DIMM and x8
configuration DRAM based DIMM are mixed on the board. Read Data Strobe, is the feature for the only x8 configura-
tion DRAMs. When Read Data Strobe is enabled by issuing a Extended Mode Register Set command with bit A11 to set
to zero, data out - DQ0~3 alligned with DQS and DQ4~7 alligned with RDQS. When write case, input on RDQS is
ignored by DRAM.
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