參數(shù)資料
型號: HY5PS12823LF
英文描述: 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
中文描述: 64Mx8 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M
文件頁數(shù): 47/66頁
文件大?。?/td> 862K
代理商: HY5PS12823LF
Rev. 0.52/Nov. 02 47
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
Write Burst Interrupt Opeation
Write burst interrupt functions is only allowed on a burst of 8. Interrupting a burst of 4 is prohibited. Write burst of 8
can only be interrupted by another Write command. Write burst interruption by Read command or Precharge com-
mand is prohibited. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write
burst interrupt timings are prohibited. Write burst interruption is allowed to any bank inside DRAM. Write burst with
Auto Precharge enabled is not allowed to be interrupted. Write burst interruption is allowed by a Write with Auto Pre-
charge command. All command timings are referenced to burst length set in the mode register. They are not refer-
enced to actual burst. For example, Minimum Write to Precharge timing is WL+BL/2+tWR where tWR starts with the
rising clock after the un-interrupted burst end and not from the end of actual burst end.
tRCD=4CLKs, CAS latency=4CLKs, Additive Latency=3CLKs BL=8
/CK
CK
tRCD=4clks, CL=4clks
AL=3clk
Active
Bank A
Write
Bank A
Write latency = 6clks
Additive Latency = 3clks
CMD
Write
Bank A’
DQS
DQ
D0 D1 D2 D3 D0’ D1’ D2’ D3’
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