參數(shù)資料
型號(hào): HY5PS12823LF
英文描述: 64Mx8|1.8V|8K|D43/D44/D54/D55|DDR II SDRAM - 512M
中文描述: 64Mx8 | 1.8 | 8K的| D43/D44/D54/D55 |的DDR II內(nèi)存- 512M
文件頁(yè)數(shù): 51/66頁(yè)
文件大?。?/td> 862K
代理商: HY5PS12823LF
Rev. 0.52/Nov. 02 51
HY5PS12423(L)F
HY5PS12823(L)F
HY5PS121623(L)F
Read with Auto Precharge
If A10 is high when read command is issued, DRAM perform read with auto precharge. When read with auto pre-
charge command is issued, internal Precharge start automatically. If tRAS minimum is satisfied, internal precharge
start at AL+BL/2 cycles later. If tRAS minimum is not satisfied, internal precharge starting point is delayed until tRAS
minimum is satisfied. A new active command can be issued to the same bank if the following two conditions are satis-
fied simultaneously.
1. The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.
2. The RAS cycle time (tRC) from the previous bank activation has been satisfied.
/CK
CK
Read w/ AP
Bank A
Q0 Q1 Q2 Q3
Read latency = 6clks
CMD
DQS
DQ
Active
Bank A
tRP
tRCD=4CLKs, tRP=4CLK, BL=4, CL=4CLKs, AL=2CLKs (tRP limit)
Auto Precharge Start
tRC min.
tRAS min.
/CK
CK
Read w/AP
Bank A
Q0 Q1 Q2 Q3
Read latency = 6clks
CMD
DQS
DQ
Active
tRP
tRCD=4CLKs, tRP=4CLK, BL=4, CL=4CLKs, AL=2CLKs (tRC limit)
Auto Precharge Start
tRC min.
tRAS min.
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