
32
ICS1890
10Base-T Operations Register (register 18 [0x12])
10Base-T Operations Register (register 18)
This register contains all of the extra status and control bits
required for 10Base-T operation.
Bits Reserved for ICS use (15, 13, 6)
These bits are reserved for ICS use. These bits should only be
written as logic zero. Writing a logic one to these bits may
prevent the device from operating correctly. The value of
these bits is unspecified and may be a logic zero or one.
Polarity Reversed (bit 14)
This bit is set to a logic one if the polarity of the receive data
pair is reversed. This bit will be a logic zero if the polarity is
correct.
Jabber Inhibit (bit 5)
Setting this bit to a logic one turns off the internal check for
transmit jabber. When the jabber check is disabled, no action
occurs when transmissions are longer than the jabber timer
value. When this bit is set to a logic zero normal 10Base-T
jabber checking is enabled.
Bit Reserved for ICS use (bit 4)
This bit must be written to a 1. The read value of this bit is
undefined.
Auto Polarity Inhibit (bit 3)
When this bit is set to a logic one, correction for reversed
receive data wires is disabled. When this bit is set to a logic
Zero, reversed receive data wires are automatically corrected
for internally.
Bit
Definition
When bit=0
When bit=1
Access
Default
Hex
15
Reserved for ICS
Read unspecified
must be wirtten as a 0
RW /0
0
14
Polarity Reversed
polarity normal
polarity reserved
RO
/LH
0
13
Reserved for ICS
Read unspecified
RW /0
-
12
Reserved for ICS
Read unspecified
RW /0
-
11
Reserved for ICS
Read unspecified
RW /0
-
10
Reserved for ICS
Read unspecified
RW /0
-
9
Reserved for ICS
Read unspecified
RW /0
-
8
Reserved for ICS
Read unspecified
RW /0
-
7
Reserved for ICS
Read unspecified
RW /0
-
6
Reserved for ICS
Read unspecified
RW /0
-
5
Jabber Inhibit
normal jabber behavior
no jabber check
RW
0
4
Reserved for ICS
Read unspecified
must be written as a 1
RW /1
1
3
Auto Polarity Inhibit
polarity automatically corrected
polarity not corrected
RW
0
2
SQE Test Inhibit
normal SQE test behavior
no SQE test
RW
0
1
Link Loss Inhibit
normal Link Loss behavior
link always = Link Pass
RW
0
Squelch Inhibit
normal Squelch
no Squelch
RW
0