- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67685 > ICS1890Y-14 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
| 型號： | ICS1890Y-14 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 37/66頁 |
| 文件大?。?/td> | 1749K |
| 代理商： | ICS1890Y-14 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當(dāng)前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
42
ICS1890
Collision Detected
10COL/(COL)
The ICS1890 asserts Collision Detected (COL) when it
detects a receive carrier (non idle condition while transmitting
(TXEN asserted).
In the 10 Mbps mode, the non-idle condition is detected by
monitoring the un-squelched receive signal. COL is not
synchronous to either the transmit or receive clocks.
In full duplex mode, COL is disabled and always remains low.
In the 10 Mbps Node mode, COL will also be asserted as part
of the signal quality error test (SQE). This behavior can be
suppressed with the SQE Test Inhibit bit (18:2).
Link Pulse Interface
Link Pulse Interface - Pin Mapping
When the ICS1890 is operating in the Link Pulse mode, the
MII Data Interface is remapped to accommodate the Link
PulseInterface.Thefollowingtabledetailstheexactpinmapping.
Each individual pin description also contains the new Link
Pulse Interface pseudo pin name followed by the real MII
Data Interface pin name that it is mapped onto.
MII
Link Pulse
TXCLK
LTCLK
TXEN
TXER
LPTX
TXD3
TXD2
XD1
TXD0
RXCL
KLRCLK
RXDV
RXER
LPRX
RXD3
RXD2
RXD1
RXD0
CRS
COL
LSTA
SD
Other mode configuration pins behave identically regardless
of which data interface is used.
Transmit Clock
LTCLK/(TXCLK)
The Transmit Clock (10TCLK) is a continuous clock signal
generated by the ICS1890 with a frequency of 25 MHz.
Transmit Link Pulse
LPTX/(TXER)
Data presented on this input will be transmitted as a Link Pulse
of approximately the same duration.
Receive Clock
LRCLK/(RXCLK)
The Receive Clock (LRCLK) is sourced by the ICS1890 and
is 25 MHz in frequency.
Receive Link Pulse
LPRX/(RXER)
Receive activity that is qualified as a Link Pulse will be output
on this pin as a high level of approximately the same duration
as the Link Pulse.
Signal Detect
SD/(LSTA)
This signal is asserted when the PLL detects 100Base-T activity
on the receive channel.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS2059GI-02 | 27 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| ICS2304NZGI-1T | 2304 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS2304NZG-1LF | 2304 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS252MI-XXLF | 200 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS252MI-XX | 200 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1890Y-4 | 制造商:ICS 功能描述:1890Y-4 |
| ICS1891 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
| ICS1891Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
| ICS1892 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。