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參數(shù)資料
| 型號(hào)： | ICS1890Y-14 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 45/66頁 |
| 文件大?。?/td> | 1749K |
| 代理商： | ICS1890Y-14 |
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5
ICS1890
The ICS1890 is designed to allow hot insertion of an MII
cable into a MAC MII port. During the power-up phase, the
ICS1890 will isolate the MII and the Twisted Pair Transmit
signal pair
100M Stream Interface
The 100M Stream Interface is an alternative parallel interface
between the PHY and MAC/Repeater than the standard MII
Data interface. The Stream Interface provides a lower level
interface and, therefore, lower bit delay than the standard MII
Data Interface.
This interface is selected by setting the MII/SI pin to STREAM
INTERFACE mode and by setting the 10/100SEL pin to 100
mode.
The Stream Interface bypasses the Physical Coding Sublayer
(PCS) and provides a direct unscrambled, unframed 5-bit
interface to the Physical Media Access (PMA) layer.
The Stream Interface consists of a 14 signal interface: STCLK,
STD[4:0], SRCLK, SRD[4:0], SCRS, SD.
Data is exchanged between the MAC and PHY using 5-bit
unframed code groups at 25 MHz clock rate.
The Stream Interface provides a CRS signal by continuing to
use the logic that is bypassed by this interface. This gives a
carrier indication faster than is possible from the MAC/Repeater
since the bits are examined serially as soon as they enter the
PHY.
Since only the Stream Interface or the MII Interface is active
at once, it is possible to share the MII Data interface pins for
Stream Interface functionality.
The pins have the following mapping:
MII
Stream
TXCLK
STCLK
TXEN
(1)
TXER
STD4
TXD3
STD3
TXD2
STD2
TXD1
STD1
TXD0
STD0
RXCLK
SRCLK
RXDV
(2)
RXER
SRD4
RXD3
SRD3
RXD2
SRD2
RXD1
SRD1
RXD0
SRD0
CRS
SCRS
COL
(3)
LSTA
SD
(1) 100Base-TX is a continuous transmission system and the
MAC/Repeater is responsible for sourcing IDLE symbols
when it is not transmitting data when using the Stream Interface.
(2) Since data is not framed when this interface is used, RXDV
has no meaning.
(3) Since the MAC/Repeater is responsible for sourcing both
active and idle data, the PHY can not tell when it is transmitting
in the traditional sense, so no collisions can be detected.
Other mode configuration pins behave identically regardless
of which data interface is used.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1890Y-4 | 制造商:ICS 功能描述:1890Y-4 |
| ICS1891 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
| ICS1891Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
| ICS1892 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
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