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參數(shù)資料
| 型號： | ICS1890Y-14 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 9/66頁 |
| 文件大小： | 1749K |
| 代理商： | ICS1890Y-14 |
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17
ICS1890
Management Interface
The ICS1890 provides a management interface to connect to
a management entity. The two wire serial interface is part of
the MII and is described in the MII section. The interface
allows the transport of status information from the ICS1890
tothemanagement entityandthetransport ofcontrol information
to the ICS1890. It includes a register set, a frame format, and
a protocol.
Management Register Set
The register set includes the mandatory basic control and
status registers and an extended set. TheICS1890implements
the following registers.
Control
(register 0)
Status
(register 1)
PHYIdentifier
(register 2)
PHYIdentifier
(register 3)
Auto-Negotiation Advertisement
(register 4)
Auto-Negotiation Link Partner Ability
(register 5)
Auto-Negotiation Expansion
(register 6)
Reserved by IEEE
(registers 7-15)
Extended Control
(register 16)
QuickPoll Status
(register 17)
10Base-T Operations
(register 18)
Extended Control 2
(register 19)
Reserved by ICS
(registers 20-31)
Management Frame Structure
The management interface uses a serial bit stream with a
specified frame structure and protocol as defined below.
Preamble
11...11
(32 ones)
SOF
01
(2 bits)
Op Code
10 (read), 01 (write)
(2 bits)
Address
AAAAA
(5 bits)
Register
RRRRR
(5 bits)
TA
NN
(2 bits)
Data
DD...DD
(16 bits)
Idle
Zo
high impedance
Preamble
The ICS1890 looks for a pattern of 32 logic ones followed by
the SOF delimiter before responding to a transaction.
Start of Frame
Following the preamble a start of frame delimiter of zero-one
initiates a transaction.
Operation Code The valid codes are 10 for a read operation
and 01 for a write operation. Other codes are ignored.
Address
There may be up to 32 PHYs attached to the MII. This 5 bit
address is compared to the internal address of the ICS1890,
as set by the P[0...4]* pins, for a match.
Register Address
The ICS1890 uses this field to select one of the registers
within the set. If a non-existent register is specified, the
ICS1890 ignores the command.
TA
This 2-bit field is used by the ICS1890 to avoid contention
during read transactions. TheICS1890will remain in the high
impedance state for the first bit time and drive a logic zero for
the second bit time.
Data
This is a 16-bit field with bit 15 being the first bit sent or
received.
Idle
The ICS1890 is in the high impedance state during the idle
condition. At least one idle must occur after each write to the
device. No idles are required after a read.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1890Y-4 | 制造商:ICS 功能描述:1890Y-4 |
| ICS1891 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
| ICS1891Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
| ICS1892 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
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