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參數(shù)資料
| 型號(hào)： | ICS1890Y-14 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 40/66頁 |
| 文件大?。?/td> | 1749K |
| 代理商： | ICS1890Y-14 |
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45
ICS1890
TP_TXTristate
TPTRI
When this pin is set to a logic zero, the twisted pair transmitter
output pins will be enabled normally to source 100Base-TX or
10Base-T data.
When this pin is set to a logic one, the twisted pair transmitter
output pins will be tristated.
MAC - PHY Receive Interface Tristate
RXTRI
When this input is a logic zero the selected MAC-PHY interface
behaves normally.
When this input is a logic one, the RXCLK, RXD[3:0], RXER,
and RXDV pins are tristated. This allows repeater designs to
bus the shared receive lines without requiring extra tristatable
buffers on each port.
Note that the CRS and COL pins are not tristated. This allows
repeater logic to use these signals to determine which receive
port to enable.
Link Status
LSTA
This output reflects the current Link Status. It is similar to bit
(1:2) but changes dynamically instead of latching on a link
failure. The output is low when the link is invalid and is high
when a valid link has been established.
When this bit is high, the 10/100SEL and DPXSEL bits can be
observed to determine what type of link has been established.
Cipher Locked Status
LOCK
This output reflects the status of the Stream Cipher decoder
block. When the Stream Cipher has not locked onto the incoming
data stream, this output will be a logic zero. When the Stream
Cipher has locked onto the incoming data stream, this output
will be a logic one.
Note that the Stream Cipher will only lock onto 100Base-TX
data (or IDLE symbols) and will not lock when 10Base-T data
is present.
System Reset
RESET~
When grounded, this pin causes the ICS1890 to enter a re-
set/ low power state. On the low to high transition of RESET,
the device will begin to complete its reset cycle. Upon
comple-tion, the ICS1890 will be initialized its default state.
While this pin is held low, the device is kept in its low power
mode. Power savings and timings are shown in the Electricals
section.
LED/PHY Address Usage
The ICS1890 device uses a unique pin sharing scheme that
allows the 5 LED pins to also be used to set the PHY address.
At power-up and reset they define the MII PHY address of the
device. Subsequent to power-up and reset, they become LED
status indicators.
The PHY address can be any number between 0 and 31. When
PHY address 0 is used, the devices MII interface starts out
Isolated and must be enabled through the MII management
port (Reg 0 bit 10), as defined by the IEEE specification. All
other addresses leave the MII interface active.
The actual value used for the individual PHY address bits
depends on the configuration of the LED components. This is
shown in the figure below. When a 1 value is desired the
LED and resistor are connected between the LED pin and Vdd
(LED Pin X). When a 0 value is desired the LED and resistor
are connected between the LED pin and Ground (LED Pin Y).
The special driver will sense the polarity and adjust its drive
logic to appropriately turn the LED light on or off.
Resistor values should be in the range of 510 to 10k. A
1k resistor is recommended.
If LEDs are not required for the application, only a resistor is
required to set the PHY address.
If LEDs are not required for the application and the ICS1890
will not be accessed with the serial MII management interface,
then only a single resistor to VDD on any one of the LED pins
is required. This will ensure that the PHY address is not zero,
which would cause the ICS1890 to power up in the isolated
state with no way for management to enable the MII interface.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1890Y-4 | 制造商:ICS 功能描述:1890Y-4 |
| ICS1891 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
| ICS1891Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
| ICS1892 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1892Y | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
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