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參數(shù)資料
| 型號(hào)： | ID8259A |
| 廠商： | Intel Corp. |
| 英文描述： | PROGRAMMABLE INTERRUPT CONTROLLER |
| 中文描述： | 可編程中斷控制器 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 325K |
| 代理商： | ID8259A |
8259A
NOTES:
1. Master clear active only during ICW1.
2. FREEZE is active during INTA and poll sequences only.
3. Truth Table for a D-Latch.
C
D
Q
Operation
231468–22
1
0
Di
X
Di
Follow
Hold
Qn-1
Figure 9. Priority CellDSimplified Logic Diagram
The following registers can be read via OCW3 (IRR
and ISR or OCW1
[
IMR
]
).
Interrupt Request Register (IRR): 8-bit register which
contains the levels requesting an interrupt to be ac-
knowledged. The highest request level is reset from
the IRR when an interrupt is acknowledged. (Not af-
fected by IMR.)
In-Service Register (ISR): 8-bit register which con-
tains the priority levels that are being serviced. The
ISR is updated when an End of Interrupt Command
is issued.
Interrupt Mask Register: 8-bit register which con-
tains the interrupt request lines which are masked.
The IRR can be read when, prior to the RD pulse, a
Read Register Command is issued with OCW3 (RR
e
1, RIS
e
0.)
The ISR can be read, when, prior to the RD pulse, a
Read Register Command is issued with OCW3 (RR
e
1, RIS
e
1).
There is no need to write an OCW3 before every
status read operation, as long as the status read
corresponds with the previous one; i.e., the 8259A
‘‘remembers’’ whether the IRR or ISR has been pre-
viously selected by the OCW3. This is not true when
poll is used.
After initialization the 8259A is set to IRR.
For reading the IMR, no OCW3 is needed. The out-
put data bus will contain the IMR whenever RD is
active and A0
e
1 (OCW1).
Polling overrides status read when P
e
1, RR
e
1
in OCW3.
Edge and Level Triggered Modes
This mode is programmed using bit 3 in ICW1.
If LTIM
e
‘0’, an interrupt request will be recognized
by a low to high transition on an IR input. The IR
input can remain high without generating another in-
terrupt.
17
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