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參數(shù)資料
| 型號： | ID8259A |
| 廠商： | Intel Corp. |
| 英文描述： | PROGRAMMABLE INTERRUPT CONTROLLER |
| 中文描述： | 可編程中斷控制器 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 325K |
| 代理商： | ID8259A |
8259A
THE CASCADE BUFFER/COMPARATOR
This function block stores and compares the IDs of
all 8259A’s used in the system. The associated
three I/O pins (CAS0-2) are outputs when the 8259A
is used as a master and are inputs when the 8259A
is used as a slave. As a master, the 8259A sends
the ID of the interrupting slave device onto the
CAS0–2 lines. The slave thus selected will send its
preprogrammed subroutine address onto the Data
Bus during the next one or two consecutive INTA
pulses. (See section ‘‘Cascading the 8259A’’.)
INTERRUPT SEQUENCE
The powerful features of the 8259A in a microcom-
puter system are its programmability and the inter-
rupt routine addressing capability. The latter allows
direct or indirect jumping to the specific interrupt rou-
tine requested without any polling of the interrupting
devices. The normal sequence of events during an
interrupt depends on the type of CPU being used.
The events occur as follows in an MCS-80/85 sys-
tem:
1. One or more of the INTERRUPT REQUEST lines
(IR7–0) are raised high, setting the correspond-
ing IRR bit(s).
2. The 8259A evaluates these requests, and sends
an INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds
with an INTA pulse.
4. Upon receiving an INTA from the CPU group, the
highest priority ISR bit is set, and the correspond-
ing IRR bit is reset. The 8259A will also release a
CALL instruction code (11001101) onto the 8-bit
Data Bus through its D7–0 pins.
5. This CALL instruction will initiate two more INTA
pulses to be sent to the 8259A from the CPU
group.
6. These two INTA pulses allow the 8259A to re-
lease its preprogrammed subroutine address
onto the Data Bus. The lower 8-bit address is re-
leased at the first INTA pulse and the higher 8-bit
address is released at the second INTA pulse.
7. This completes the 3-byte CALL instruction re-
leased by the 8259A. In the AEOI mode the ISR
bit is reset at the end of the third INTA pulse.
Otherwise, the ISR bit remains set until an appro-
priate EOI command is issued at the end of the
interrupt sequence.
The events occuring in an 8086 system are the
same until step 4.
4. Upon receiving an INTA from the CPU group, the
highest priority ISR bit is set and the correspond-
ing IRR bit is reset. The 8259A does not drive the
Data Bus during this cycle.
5. The 8086 will initiate a second INTA pulse. Dur-
ing this pulse, the 8259A releases an 8-bit pointer
onto the Data Bus where it is read by the CPU.
6. This completes the interrupt cycle. In the AEOI
mode the ISR bit is reset at the end of the sec-
ond INTA pulse. Otherwise, the ISR bit remains
set until an appropriate EOI command is issued
at the end of the interrupt subroutine.
If no interrupt request is present at step 4 of either
sequence (i.e., the request was too short in duration)
the 8259A will issue an interrupt level 7. Both the
vectoring bytes and the CAS lines will look like an
interrupt level 7 was requested.
When the 8259A PIC receives an interrupt, INT be-
comes active and an interrupt acknowledge cycle is
started. If a higher priority interrupt occurs between
the two INTA pulses, the INT line goes inactive im-
mediately after the second INTA pulse. After an un-
specified amount of time the INT line is activated
again to signify the higher priority interrupt waiting
for service. This inactive time is not specified and
can vary between parts. The designer should be
aware of this consideration when designing a sys-
tem which uses the 8259A. It is recommended that
proper asynchronous design techniques be fol-
lowed.
7
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