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參數(shù)資料
| 型號： | ID8259A |
| 廠商： | Intel Corp. |
| 英文描述： | PROGRAMMABLE INTERRUPT CONTROLLER |
| 中文描述： | 可編程中斷控制器 |
| 文件頁數(shù)： | 24/24頁 |
| 文件大?。?/td> | 325K |
| 代理商： | ID8259A |
8259A
WAVEFORMS
(Continued)
INTA SEQUENCE
231468–30
NOTES:
Interrupt output must remain HIGH at least until leading edge of first INTA.
1. Cycle 1 in 8086, 8088 systems, the Data Bus is not active.
Data Sheet Revision Review
The following changes have been made since revision 2 of the 8259A data sheet.
1. The first paragraph of the Poll Command section was rewritten to clarify the status of the INT pin.
2. A paragraph was added to the Interrupt Sequence section to indicate the status of the INT pin during
multiple interrupts.
3. A reference to PLCC packaging was added.
4. All references to the 8259A-8 have been deleted.
INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080
INTEL CORPORATION (U.K.) Ltd., Swindon, United Kingdom; Tel. (0793) 696 000
INTEL JAPAN k.k., Ibaraki-ken; Tel. 029747-8511
Printed in U.S.A./xxxx/1196/B10M/xx xx
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