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參數(shù)資料
| 型號(hào)： | ID8259A |
| 廠商： | Intel Corp. |
| 英文描述： | PROGRAMMABLE INTERRUPT CONTROLLER |
| 中文描述： | 可編程中斷控制器 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大小： | 325K |
| 代理商： | ID8259A |
8259A
231468–7
Figure 4c. 8259A Block Diagram
231468–8
Figure 5. 8259A Interface to
Standard System Bus
INTERRUPT SEQUENCE OUTPUTS
MCS-80, MCS-85
This sequence is timed by three INTA pulses. During
the first INTA pulse the CALL opcode is enabled
onto the data bus.
Content of First Interrupt Vector Byte
D7 D6 D5 D4 D3 D2 D1 D0
CALL CODE
1
1
0
0
1
1
0
1
During the second INTA pulse the lower address of
the appropriate service routine is enabled onto the
data bus. When Interval
e
4 bits A
5
–A
7
are pro-
grammed, while A
0
–A
4
are automatically inserted by
the 8259A. When Interval
e
8 only A
6
and A
7
are
programmed, while A
0
–A
5
are automatically insert-
ed.
8
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