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參數(shù)資料
| 型號(hào)： | ID8259A |
| 廠商： | Intel Corp. |
| 英文描述： | PROGRAMMABLE INTERRUPT CONTROLLER |
| 中文描述： | 可編程中斷控制器 |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 325K |
| 代理商： | ID8259A |
8259A
A.C. CHARACTERISTICS
T
A
e
0
§
C to 70
§
C, V
CC
e
5V
g
10%
TIMING REQUIREMENTS
Symbol
Parameter
8259A
8259A-2
Units
Test Conditions
Min
Max
Min
Max
TAHRL
AO/CS Setup to RD/INTA
v
AO/CS Hold after RD/INTA
u
0
0
ns
TRHAX
0
0
ns
TRLRH
RD Pulse Width
AO/CS Setup to WR
v
AO/CS Hold after WR
u
235
160
ns
TAHWL
0
0
ns
TWHAX
0
0
ns
TWLWH
WR Pulse Width
Data Setup to WR
u
Data Hold after WR
u
290
190
ns
TDVWH
240
160
ns
TWHDX
0
0
ns
TJLJH
Interrupt Request Width (Low)
100
100
ns
See Note 1
TCVIAL
Cascade Setup to Second or Third
INTA
(Slave Only)
55
40
ns
TRHRL
End of RD to Next RD
End of INTA to Next INTA within
an INTA Sequence Only
160
100
ns
TWHWL
End of WR to Next WR
190
100
ns
*
TCHCL
End of Command to Next Command
(Not Same Command Type)
500
150
ns
End of INTA Sequence to Next
INTA Sequence.
*
Worst case timing for TCHCL in an actual microprocessor system is typically much greater than 500 ns (i.e. 8085A
e
1.6
m
s, 8085A-2
e
1
m
s, 8086
e
1
m
s, 8086-2
e
625 ns)
500
300
NOTE:
This is the low time required to clear the input latch in the edge triggered mode.
TIMING RESPONSES
Symbol
Parameter
8259A
8259A-2
Units
Test Conditions
Min
Max
Min
Max
TRLDV
Data Valid from RD/INTA
v
200
120
ns
C of Data Bus
e
100 pF
TRHDZ
Data Float after RD/INTA
u
10
100
10
85
ns
C of Data Bus
Max Test C
e
100 pF
Min Test C
e
15 pF
TJHIH
Interrupt Output Delay
Cascade Valid from First INTA
v
(Master Only)
Enable Active from RD
v
or INTA
v
Enable Inactive from RD
u
or INTA
u
350
300
ns
TIALCV
565
360
ns
C
INT
e
100 pF
TRLEL
125
100
ns
C
CASCADE
e
100 pF
TRHEH
150
150
ns
TAHDV
Data Valid from Stable Address
200
200
ns
TCVDV
Cascade Valid to Valid Data
300
200
ns
21
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