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參數(shù)資料
| 型號： | IDT79R4700-100G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 100 MHz, RISC PROCESSOR, CPGA179 |
| 封裝： | PGA-179 |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 437K |
| 代理商： | IDT79R4700-100G |
IDT79R4700/RV4700
COMMERCIAL TEMPERATURE RANGE
2
DESCRIPTION
The IDT79R4700 64-bit RISC Microprocessor is both
software and pin-compatible with the R4XXX processor
family. With 64-bit processing capabilities, the R4700
provides more computational power and data movement
bandwidth than is delivered to typical embedded systems
by 32-bit processors.
Through quick interrupt response times, fast algorithm
execution speeds, and the ability to manipulate packet
headers and make routing decisions quickly, the R4700
offers ideal internetworking solutions that are crucial for
high-speed data switches and routers.
The R4700 is upwardly software compatible with the
IDT79R3000microprocessor family, including the
IDT RISController79R3051/R3052/R3041/R3081/
as well as the R4640/R4650 and R5000. An array of
development tools facilitates rapid development of R4700-
based systems, allowing a variety of customers access to
the MIPS Open Architecture philosophy.
This data sheet provides an overview of the R4700’s
CPU features and architecture. A more detailed descrip-
tion of this processor is provided in the
IDT79R4600 and
IDT79R4700 RISC Processor Hardware User’s Manual,
available from Integrated Device Technology (IDT). Infor-
mation on development support, applications notes and
complementary products is
available through your local
IDT sales representative.
Note that throughout this data sheet and any other IDT
materials for this device, the R4700 indicates a 5V part;
RV4700 designates a reduced voltage (3V) part.
DATA SHEET REVISION HISTORY
Changes to version dated January 1996:
Deleted data on 150MHz speed for 5V part only.
Changes to version dated March 1997:
Upgraded 80 to 175 MHz speed specs from “prelimi-
nary” to “final.”
Changes to version dated August 1997:
Upgraded speed to 200MHz on 3V part specs.
Added SyncOut to SyncIn Delay parameters to AC
characteristic tables.
Figure 1. R4700 Pipeline Stages
I0
1I
2I
1R
2R
1A
2A
1D
2D
1W
2W
I1
1I
2I
1R
2R
1A
2A
1D
2D
1W
2W
I2
1I
2I
1R
2R
1A
2A
1D
2D
1W
I3
1I
2I
1R
2R
1A
2A
1D
I4
1I
2I
1R
2R
1A
one cycle
Key to Figure
1I-1R
Instruction cache access
2I
Instruction virtual-to-physical address translation in ITLB
2A-2D
Data cache access and load align
1D
Data virtual-to-physical address translation in DTLB
1D-2D
Virtual-to-physical address translation in JTLB
2R
Register file read
2R
Bypass calculation
2R
Instruction decode
2R
Branch address calculation
1A
Issue or slip decision
1A-2A
Integer add, logical, shift
1A
Data virtual address calculation
2A
Store align
1A
Branch decision
2W
Register file write
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