參數(shù)資料
型號(hào): IDT79R4700-100G
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: 64-BIT, 100 MHz, RISC PROCESSOR, CPGA179
封裝: PGA-179
文件頁(yè)數(shù): 3/25頁(yè)
文件大?。?/td> 437K
代理商: IDT79R4700-100G
IDT79R4700/RV4700
COMMERCIAL TEMPERATURE RANGE
11
VCCPI
Quiet VCC for PLL
Quiet VCC for the internal phase locked loop.
VSSPI
Quiet VSS for PLL
Quiet VSS for the internal phase locked loop.
Interrupt Interface
Int*(5:0)
I
Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.
NMI*
I
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 6 of the interrupt register.
Initialization Interface
VCCOkI
VCC is OK
When asserted, this signal indicates to the R4700 that the power supply has been above
the Vcc minimum for more than 100 milliseconds and will remain stable. The assertion
of VCCOk initiates the reading of the boot-time-mode-control serial stream.
ColdReset*
I
Cold reset
This signal must be asserted for a power on reset or a cold reset. The clocks SClock,
TClock, and RClock begin to cycle and are synchronized with the de-assertion edge of
ColdReset. ColdReset must be de-asserted synchronously with MasterOut.
Reset*
I
Reset
This signal must be asserted for any reset sequence. It may be asserted synchronously
or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset must
be de-asserted synchronously with MasterOut.
ModeClock
O
Boot-mode clock
Serial boot-mode data clock output at the system clock frequency divided by two hun-
dred fifty-six.
ModeIn
I
Boot-mode data in
Serial boot-mode data input.
Pin Name
Type
Description
Table 4. Pin Descriptions (Page 2 of 2)
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