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參數(shù)資料
| 型號： | IDT79R4700-100G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 100 MHz, RISC PROCESSOR, CPGA179 |
| 封裝： | PGA-179 |
| 文件頁數(shù)： | 23/25頁 |
| 文件大小： | 437K |
| 代理商： | IDT79R4700-100G |
IDT79R4700/RV4700
COMMERCIAL TEMPERATURE RANGE
7
external device. Therefore, either a low cost interface
requiring no read or write buffering or a faster, high perfor-
mance interface can be designed to communicate with the
R4700. Again, the system designer has the flexibility to
make these price/performance trade-offs.
System Command Bus
The R4700 interface has a 9-bit System Command
(SysCmd) bus. The command bus indicates whether the
SysAD bus carries an address or data. If the SysAD carries
an address, then the SysCmd bus also indicates what type
of transaction is to take place (for example, a read or write).
If the SysAD carries data, then the SysCmd bus also gives
information about the data (for example, this is the last data
word transmitted, or the cache state of this data line is
clean exclusive). The SysCmd bus is bidirectional to
support both processor requests and external requests to
the R4700. Processor requests are initiated by the R4700
and responded to by an external device. External requests
are issued by an external device and require the R4700 to
respond.
The R4700 supports one to eight byte and block trans-
fers on the SysAD bus. In the case of a sub-doubleword
transfer, the low-order three address bits give the byte
address of the transfer, and the SysCmd bus indicates the
number of bytes being transferred.
Handshake Signals
There are six handshake signals on the system inter-
face. Two of these, RdRdy* and WrRdy* are used by an
external device to indicate to the R4700 whether it can
accept a new read or write transaction. The R4700
samples these signals before deasserting the address on
read and write requests.
ExtRqst* and Release* are used to transfer control of
the SysAD and SysCmd buses between the processor and
an external device. When an external device needs to
control the interface, it asserts ExtRqst*. The R4700
responds by asserting Release* to release the system
interface to slave state.
ValidOut* and ValidIn* are used by the R4700 and the
external device respectively to indicate that there is a valid
command or data on the SysAD and SysCmd buses. The
R4700 asserts ValidOut* when it is driving these buses with
a valid command or data, and the external device drives
ValidIn* when it has control of the buses and is driving a
valid command or data.
Non-overlapping System Interface
The R4700 bus uses a non-overlapping system inter-
face. This means that only one processor request may be
outstanding at a time and that the request must be serviced
by an external device before the R4700 issues another
request. The R4700 can issue read and write requests to
an external device, and an external device can issue read
and write requests to the R4700.
For processor read transaction the R4700 asserts
ValidOut* and simultaneously drives the address and read
command on the SysAD and SysCmd buses. If the system
interface has RdRdy* asserted, then the processor tristates
its drivers and releases the system interface to slave state
by asserting Release*. The external device can then begin
sending the data.
Figure 5 on page 9 shows a processor block read
request and the external agent read response. The read
latency is four cycles (ValidOut* to ValidIn*), and the
response data pattern is DDxxDD. Figure 6 on page 9
shows a processor block write.
Write Reissue and Pipeline Write
The R4700 implements additional write protocols that
have been designed to improve performance. This imple-
mentation doubles the effective write bandwidth. The write
re-issue has a high repeat rate of two cycles per write. A
write issues if WrRdy* is asserted two cycles earlier and is
still asserted at the issue cycle. If it is not still asserted, the
last write re-issues again. Pipelined writes have the same
two cycle per write repeat rate but can issue one additional
write after WrRdy* de-asserts. They still follow the issue
rule as R4x00 mode for other writes.
External Requests
The R4700 responds to requests issued by an external
device. The requests can take several forms. An external
device may need to supply data in response to an R4700
read request or it may need to gain control over the system
interface bus to access other resources which may be on
that bus. It also may issue requests to the processor, such
as a request for the R4700 to write to the R4700 interrupt
register. The R4700 supports Write, Null, and Read
Response external requests.
Boot-Time Options
Fundamental operational modes for the processor are
initialized by the boot-time mode control interface. The
boot-time mode control interface is a serial interface operat-
ing at a very low frequency (MasterClock divided by 256).
The low-frequency operation allows the initialization infor-
mation to be kept in a low-cost seriel EEPROM; alterna-
tively, the 20-or-so bits could be generated by the system
interface ASIC or a simple PAL.
Immediately after the VCCOK
signal is asserted, the
processor reads a bit stream of 256 bits to initialize all fun-
damental operational modes. After initialization is complete,
the processor continues to drive the serial clock output, but
no further initialization bits are read.
JTAG Interface
The R4700 supports the JTAG interface pins, with the
serial input connected to serial output. Boundary scan is
not supported.
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