參數(shù)資料
型號(hào): IDT79R4700-100G
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: 64-BIT, 100 MHz, RISC PROCESSOR, CPGA179
封裝: PGA-179
文件頁(yè)數(shù): 24/25頁(yè)
文件大小: 437K
代理商: IDT79R4700-100G
IDT79R4700/RV4700
COMMERCIAL TEMPERATURE RANGE
8
Boot-Time Modes
The boot-time serial mode stream is defined in
Table 3. Bit 0 is the first bit presented to the processor
when VCCOK is asserted; bit 255 is the last.
Power Management
CP0 is also used to control the power manage-
ment for the R4700. This is the standby mode and can
be used to reduce the power consumption of the
internal core of the CPU. Standby mode is entered by
executing the WAIT instruction with the SysAD bus
idle and is exited by an interrupt.
Table 3. Boot-time Mode Stream
Mode bit
Description
Mode
bit
Description
0
reserved (must be zero)
14:13
Output driver strength
10
→ 100% strength (fastest),
11
→ 83% strength,
00
→ 67% strength,
01
→ 50% strength (slowest)
4:1
Writeback data rate
0
→ D,
1
→ DDx,
2
→ DDxx,
3
→ DxDx,
4
→ DDxxx,
5
→ DDxxxx,
6
→ DxxDxx,
7
→ DDxxxxxx,
8
→ DxxxDxxx,
9-15 reserved
bit 15
0 -> TClock[0] enabled
1 -> TClock[0] disabled
7:5
Clock divisor
0
→ 2,
1
→ 3,
2
→ 4,
3
→ 5,
4
→ 6,
5
→ 7,
6
→ 8,
7 reserved
bit 16
0 -> TClock[1] enabled
1 -> TClock[1] disabled
80
→ Little endian,
1
→ Big endian
bit 17
0 -> RClock[0] enabled
1 -> RClock[0] disabled
10:9
00
→ R4000 compatible,
01
→ reserved,
10
→ pipelined writes,
11
→ write re-issue
bit 18
0 -> RClock[1] enabled
1 -> RClock[1] disabled
11
Disable the timer interrupt on Int[5].
0
→ Enabled
1
→ Disabled
255:19
Reserved (must be zero)
12
reserved (must be zero)
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