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參數(shù)資料
| 型號： | IDT79R4700-100G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 100 MHz, RISC PROCESSOR, CPGA179 |
| 封裝： | PGA-179 |
| 文件頁數(shù)： | 22/25頁 |
| 文件大?。?/td> | 437K |
| 代理商： | IDT79R4700-100G |
IDT79R4700/RV4700
COMMERCIAL TEMPERATURE RANGE
6
Cache Memory
To keep the R4700’s high-performance pipeline full and
operating efficiently, the R4700 incorporates on-chip
instruction and data caches that can be accessed in a
single processor cycle. Each cache has its own 64-bit data
path and can be accessed in parallel.
Instruction Cache
The R4700 incorporates a two-way set associative on-
chip instruction cache. This virtually indexed, physically
tagged cache is 16KB in size and is protected with word
parity.
Because the cache is virtually indexed, the virtual-to-
physical address translation occurs in parallel with the
cache access, further increasing performance by allowing
these two operations to occur simultaneously. The tag
holds a 24-bit physical address and valid bit and is parity
protected.
The instruction cache is 64-bits wide and can be
refilled or accessed in a single processor cycle. For a peak
instruction bandwidth of 800MB/sec at 200MHz, instruction
fetches require only 32 bits per cycle. To reduce power
dissipation, sequential accesses take advantage of the 64-
bit fetch. To minimize the cache miss penalty, cache miss
refill writes use 64 bits-per-cycle, and to maximize perfor-
mance, the line size is eight instructions (32 bytes).
Data Cache
For fast, single cycle data access, the R4700 includes
a 16KB on-chip data cache that is two-way set associative
with a fixed 32-byte (eight words) line size.
The data cache is protected with byte parity and its tag
is protected with a single parity bit. It is virtually indexed
and physically tagged to allow simultaneous address trans-
lation and data cache access
The normal write policy is writeback, which means that
a store to a cache line does not immediately cause memory
to be updated. This increases system performance by
reducing bus traffic and eliminating the bottleneck of
waiting for each store operation to finish before issuing a
subsequent memory operation. Software can however
select write-through on a per-page basis when it is appro-
priate, such as for frame buffers.
Associated with the data cache is the store buffer.
When the R4700 executes a Store instruction, this single-
entry buffer gets written with the store data while the tag
comparison is performed. If the tag matches, then the data
is written into the data cache in the next cycle that the data
cache is not accessed (the next non-load cycle). The store
buffer allows the R4700 to execute a store instruction every
processor cycle and to perform back-to-back stores without
penalty.
The data cache can provide 8 bytes each clock cycle,
for a peak bandwidth of 1.6 GB/sec.
Write Buffer
Writes to external memory—whether they are cache
miss writebacks, stores to uncached or write-through
addresses—use the on-chip write buffer. The write buffer
holds a maximum of four 64-bit address and 64-bit data
pairs. The entire buffer is used for a data cache writeback
and allows the processor to proceed in parallel with
memory updates.
System Interface
The R4700 supports a 64-bit system interface. This
interface operates from two clocks—TClock[1:0] and
RClock[1:0]—provided by the R4700, at some division of
the internal clock.
The system interface consists of a 64-bit Address/Data
bus with eight check bits and a 9-bit command bus
protected with parity. In addition, there are eight handshake
signals and six interrupt inputs. The interface has a simple
timing specification and is capable of transferring data
between the processor and memory at a peak rate of
500MB/sec with a 67MHz bus.
System Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used
to transfer addresses and data between the R4700 and the
rest of the system. It is protected with an 8-bit parity check
bus, SysADC.
The system interface is configurable to allow easier
interfacing to memory and I/O systems of varying frequen-
cies. The data rate and the bus frequency at which the
R4700 transmits data to the system interface are program-
mable via boot time mode control bits. Also, the rate at
which the processor receives data is fully controlled by the
0xFFFFFFFF
0xE0000000
Kernel virtual address space
(kseg3)
Mapped, 0.5GB
0xDFFFFFFF
Supervisor virtual address space
(sseg)
Mapped, 0.5GB
0xC0000000
0xBFFFFFFF
0xA0000000
Uncached kernel physical address space
(kseg1)
Unmapped, 0.5GB
0x9FFFFFFF
0x80000000
Cached kernel physical address space
(kseg0)
Unmapped, 0.5GB
0x7FFFFFF
0x00000000
User virtual address space
(useg)
Mapped, 2.0GB
Figure 4. Kernel Mode Virtual Addressing (32-bit Mode)
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