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參數(shù)資料
| 型號： | IDT79R4700-100G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 100 MHz, RISC PROCESSOR, CPGA179 |
| 封裝： | PGA-179 |
| 文件頁數(shù)： | 21/25頁 |
| 文件大小： | 437K |
| 代理商： | IDT79R4700-100G |
IDT79R4700/RV4700
COMMERCIAL TEMPERATURE RANGE
5
System Control Co-processor (CP0)
The system control co-processor in the MIPS architec-
ture is responsible for the virtual memory sub-system, the
exception control system and the diagnostics capability of
the processor. In the MIPS architecture, the system control
co-processor (and thus the kernel software) is implementa-
tion dependent.
System Control Co-Processor Registers
The
R4700
incorporates
all
system
control
co-
processor (CP0) registers, on-chip. These registers provide
the path through which the virtual memory system’s page
mapping is examined and changed, exceptions are
handled and operating modes are controlled (kernel vs.
user mode, interrupts enabled or disabled, cache features).
In addition, to aid in cache diagnostic testing and assist in
data error detection, the R4700 includes registers to imple-
ment a real-time cycle counting facility. Figure 3 on page 4
shows the R4700’s CP0 registers.
Virtual-to-Physical Address Mapping
To establish a secure environment for user processing,
the R4700 provides the user, supervisor, and kernel modes
of virtual addressing, available to system software. Bits in
a status register determine which virtual addressing mode
is used.
While in user mode, the R4700 provides a single,
uniform virtual address space of 256GB (2GB for 32-bit
address mode). When operating in the kernel mode, four
distinct virtual address spaces—totalling 1024GB (4GB in
32-bit address mode)—are simultaneously available and
are differentiated by the high-order bits of the virtual
address.
The R4700 processor also supports a supervisor mode
in which the virtual address space is 256.5GB (2.5GB in
32-bit address mode), divided into three regions that are
based on the high-order bits of the virtual address. If the
R4700 is configured for 64-bit virtual addressing, the virtual
address space layout is an upwardly compatible extension
of the 32-bit virtual address space layout. Figure 4 on
page 6 shows the address space layout for the 32-bit virtual
address operation.
Memory Management Unit (MMU)
The Memory management unit controls the virtual
memory system page mapping. It consists of an instruction
address translation buffer (the ITLB), a data address trans-
lation buffer (the DTLB), a Joint TLB (the JTLB), and co-
processor registers used for the virtual memory mapping
sub-system.
Instruction TLB (ITLB)
The R4700 also incorporates a two-entry instruction
TLB. Each entry maps a 4KB page. The instruction TLB
improves performance by allowing instruction address
translation to occur in parallel with data address translation.
When a miss occurs on an instruction address translation,
the least-recently used ITLB entry is filled from the JTLB.
The operation of the ITLB is invisible to the user.
Data TLB (DTLB)
The R4700 also incorporates a four-entry data TLB.
Each entry maps a 4KB page. The data TLB improves
performance by allowing data address translation to occur
in parallel with instruction address translation. When a miss
occurs on a data address translation, the DTLB is filled
from the JTLB. The DTLB refill is pseudo-LRU: the least
recently used entry of the least recently used half is filled.
The operation of the DTLB is invisible to the user.
Joint TLB (JTLB)
For fast virtual-to-physical address decoding, the
R4700 uses a large, fully associative TLB that maps 96
virtual pages to their corresponding physical addresses.
The TLB is organized as 48 pairs of even-odd entries and
maps a virtual address and address space identifier into
the large, 64GB physical address space.
Two mechanisms are provided to assist in controlling
the amount of mapped space and the replacement charac-
teristics of various memory regions. First, the page size can
be configured, on a per-entry basis, to map a page size of
4KB to 16MB (in multiples of 4). A CP0 register is loaded
with the page size of a mapping, and that size is entered
into the TLB when a new entry is written. Thus, operating
systems can provide special purpose maps; for example, a
typical frame buffer can be memory mapped using only one
TLB entry.
The second mechanism controls the replacement
algorithm, when a TLB miss occurs. The R4700 provides a
random replacement algorithm to select a TLB entry to be
written with a new mapping; however, the processor
provides a mechanism whereby a system specific number
of mappings can be locked into the TLB and avoid being
randomly replaced. This facilitates the design of real-time
systems, by allowing deterministic access to critical soft-
ware.
The joint TLB also contains information to control the
cache coherency protocol for each page. Specifically, each
page has attribute bits to determine whether the coherency
algorithm is uncached, non-coherent write-back, non-
coherent
write-through
write-allocate
or
non-coherent
write-through no write-allocate. Non-coherent write-back is
typically used for both code and data on the R4700;
however,
hardware-based
cache
coherency
is
not
supported.
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