參數(shù)資料
型號(hào): IDT82V2108PXG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 218/292頁(yè)
文件大?。?/td> 0K
描述: IC FRAMER T1/J1/E1 8CH 128-PQFP
標(biāo)準(zhǔn)包裝: 11
控制器類型: T1/E1/J1 調(diào)幀器
接口: 并聯(lián)
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 160mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤(pán)
其它名稱: 82V2108PXG
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IDT82V2108
T1 / E1 / J1 OCTAL FRAMER
Functional Description
21
March 5, 2009
3.4
ALARM DETECTOR (ALMD) - T1/J1 ONLY
The Alarm Detector block exists in T1/J1 mode only. It detects the
Yellow signal and the AIS (Blue Alarm) signal in SF/ESF in T1/J1 data
stream and declares the Yellow alarm, the Red alarm and the AIS alarm.
The T1 or J1 mode is selected by the J1_YEL (b5, T1/J1-02CH) while
the SF or ESF format is selected by the ESF (b4, T1/J1-02CH).
The Yellow signal is declared differently in each format:
- In T1 SF format: The Yellow signal occupies the 2nd bit of each
channel. When the occurrence of logic 1 in this bit position is less than
16 times (including 16 times) during a 40 ms period, the Yellow signal is
declared.
- In J1 SF format: The Yellow signal occupies the F-bit of the 12th
frame. When the occurrence of logic 0 on this bit position is less than 2
times (including 2 times) during a 40 ms period, the Yellow signal is
declared.
- In T1/J1 ESF format: The Yellow signal occupies the DL of the F-
bit (refer to Table 4). The pattern is ‘FF00’ in T1 mode and ‘FFFF’ in J1
mode. When the AVC (b1, T1/J1-02AH) is logic 0, the Yellow signal is
declared if 8 out of 10 successive patterns match the ‘FF00’ (in T1) or
‘FFFF’ (in J1) on the DL bit position. When the AVC (b1, T1/J1-02AH) is
logic 1, the Yellow signal is declared if 4 out of 5 successive patterns
match the ‘FF00’ (in T1) or ‘FFFF’ (in J1) on the DL bit position.
Any of the above conditions will be indicated by the YELD (b1, T1/
J1-02FH).
The AIS signal is declared when the received data is out of SF/ESF
synchronization for 60 ms and the received logic 0 is less than 127 times
in the same period. Then the AIS signal will be indicated by the AISD
(b0, T1/J1-02FH).
The Red signal is declared when one or more out of SF/ESF sync
event occurs in 40 ms. Then the Red signal will be indicated by the
REDD (b2, T1/J1-02FH).
The Yellow alarm, AIS alarm and Red alarm will be declared or
cleared when the corresponding alarm signal is present or absent for a
certain period as summarized in Table 7.
The Yellow alarm, AIS alarm and Red alarm are also the interrupt
sources in the ALMD block. When the alarm occurs, the corresponding
Interrupt Status Register (YEL, AIS or RED in b2, b0, b1 of T1/J1-02EH
respectively) will indicate the alarm. When there is any transition (from
‘0’ to ‘1’ or from ‘1’ to ‘0’) on the Interrupt Status Register, its correspond-
ing Interrupt Indication Register (YELI, AISI or REDI in b5, b3, b4 of T1/
J1-02EH respectively) will be logic 1. A transition on the Interrupt Indica-
tion Register can cause an interrupt on the INT pin if the corresponding
Interrupt Enabled Register (YELE, AISE or REDE in b2, b0, b1 of T1/J1-
02DH respectively) is logic 1.
Table 7: Alarm Summary in ALMD
Declaring
Clearing
Yellow Alarm
the Yellow signal is present for 425 ms (± 50 ms)
the Yellow signal is absent for 425 ms (± 50 ms)
AIS Alarm
the AIS signal is present for 1.5 sec (± 100 ms)
the AIS signal is absent for 16.8 sec (± 500 ms); or the AIS signal is absent for 180 ms if the
FASTD (b4, T1/J1-02DH) is set
Red Alarm
the Red signal is present for 2.55 sec (± 40 ms)
the Red signal is absent for 16.6 sec (± 500 ms); or the Red signal is absent for 120 ms if the
FASTD (b4, T1/J1-02DH) is set
相關(guān)PDF資料
PDF描述
VI-254-IX-S CONVERTER MOD DC/DC 48V 75W
IDT82V2108PX IC FRAMER T1/J1/E1 8CH 128-PQFP
VE-2TP-IX-S CONVERTER MOD DC/DC 13.8V 75W
VE-2TN-IX-S CONVERTER MOD DC/DC 18.5V 75W
PIC16LF1904-E/P MCU 7KB FLASH 256B RAM 40PDIP
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