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參數(shù)資料
| 型號： | IDT82V2108PXG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 280/292頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER T1/J1/E1 8CH 128-PQFP |
| 標(biāo)準(zhǔn)包裝： | 11 |
| 控制器類型： | T1/E1/J1 調(diào)幀器 |
| 接口： | 并聯(lián) |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 電流 - 電源： | 160mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-PQFP（14x20） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2108PXG |
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IDT82V2108
T1 / E1 / J1 OCTAL FRAMER
Functional Description
78
March 5, 2009
3.14
TRANSMIT PAYLOAD CONTROL (TPLC)
Different test patterns can be inserted in the data to be transmitted
or the data to be transmitted can be extracted to the PRBS Generator/
Detector for test in this block. The Transmit Payload Control of each
framer operates independently.
3.14.1
E1 MODE
To enable the test for the data to be transmitted, the PCCE (b0, E1-
060H) must be set to activate the setting in the indirect registers (from
20H to 7FH of TPLC indirect registers). The following methods can be
used for test on a per-TS basis:
- Selected by the PRGDSEL[2:0] (b7~5, E1-00CH), the data to be
transmitted on one of the eight framers will be extracted to the PRBS
Generator/Detector when the RXPATGEN (b2, E1-00CH) is ‘1’. The data
can be extracted in framed or unframed mode, as determined by the
UN_DET (b0, E1-00CH). In unframed mode, all 32 time slots are
extracted and the per-timeslot configuration in the TEST (b3, E1-TPLC-
indirect registers - 20~3FH) is ignored. In framed mode, the data to be
transmitted will only be extracted on the time slot configured by the
TEST (b3, E1-TPLC-indirect registers - 20~3FH). Refer to Chapter 3.12
PRBS Generator / Detector (PRGD) for details.
- Enable the payload loopback by setting the LOOP (b2, E1-TPLC-
indirect registers - 20~3FH) (refer to Chapter 3.23.3 Payload Loopback).
- Replace the data input from the TSDn/MTSD pin with the A-law or
E1-TPLC-indirect registers - 20~3FH), the DS0 (b4, E1-TPLC-indirect
registers - 20~3FH) and the DS1 (b5, E1-TPLC-indirect registers -
20~3FH) are logic 1,1,1 or 1,1,0 respectively.
- Selected by the PRGDSEL[2:0] (b7~5, E1-00CH), the test pattern
from the PRBS Generator/Detector will replace the data input from the
TSDn/MTSD pin of one of the eight framers when the RXPATGEN (b2,
E1-00CH) is ‘0’. The test pattern can replace the data in framed or
unframed mode, as determined by the UN_GEN (b1, E1-00CH). In
unframed mode, all 32 time slots are replaced and the per-timeslot con-
figuration in the TEST (b3, E1-TPLC-indirect registers - 20~3FH) is
ignored. In framed mode, the received data will only be replaced on the
time slot configured by the TEST (b3, E1-TPLC-indirect registers -
20~3FH). Refer to Chapter 3.12 PRBS Generator / Detector (PRGD) for
details.
- Replace the data input from the TSDn/MTSD pin with the value in
the IDLE[7:0] (b7~0, E1-TPLC-indirect registers - 40~5FH) when the
SUBS (b7, E1-TPLC-indirect registers - 20~3FH) and the DS0 (b4, E1-
TPLC-indirect registers - 20~3FH) are logic 1,0.
- Invert the odd bits, even bits or all bits input from the TSDn/MTSD
pin when the SUBS (b7, E1-TPLC-indirect registers - 20~3FH), the DS0
(b4, E1-TPLC-indirect registers - 20~3FH) and the DS1 (b5, E1-TPLC-
indirect registers - 20~3FH) are logic 0,0,1 or 0,1,0 or 0,1,1 respectively.
(The above methods are arranged from highest to lowest in prior-
ity.)
- Replace the signaling input from the TSSIGn pin with the value in
the A, B, C, D (b3~0, E1-TPLC-indirect registers - 61~7FH) when the
SIGSRC (b4, E1-TPLC indirect registers - 61~7FH) is logic 1 and the
Channel Associated Signaling (CAS) is chosen by the SIGEN (b6, E1-
040H) & DLEN (b5, E1-040H).
Addressed by the A[6:0] (b6~0, E1-062H), the data read from or
written into the indirect registers is in the D[7:0] (b7~0, E1-063H). The
read or write operation is determined by the R/WB (b7, E1-062H). The
indirect registers have a read/write cycle. Before the read/write opera-
tion is completed, the BUSY (b7, E1-061H) will be set. New operations
on the indirect registers can only be implemented when the BUSY (b7,
E1-061H) is cleared. The read/write cycle is 490 ns.
3.14.2
T1/J1 MODE
To enable the test for the data to be transmitted, the PCCE (b0, T1/
J1-030H) must be set to activate the setting in the indirect registers
(from 01H to 48H of TPLC indirect registers). The following methods can
be executed for test on a per-channel basis:
- Selected by the PRGDSEL[2:0] (b7~5, T1/J1-00FH), the data to
be transmitted on one of the eight framers will be extracted to the PRBS
Generator/Detector when the RXPATGEN (b2, T1/J1-00FH) is ‘1’. The
data can be extracted in framed or unframed mode, as determined by
the UN_DET (b0, T1/J1-00FH). In unframed mode, all 24 channels and
the F-bit are extracted and the per-channel configuration in the TEST
(b3, T1/J1-TPLC-indirect registers - 01~18H) is ignored. In framed
mode, the data to be transmitted will only be extracted on the channel
specified by the TEST (b3, T1/J1-TPLC-indirect registers - 01~18H).
Fractional T1/J1 data can also be extracted in the specified channel
when the Nx56k_DET (b3, T1/J1-00FH) is set. Refer to Chapter 3.12
PRBS Generator / Detector (PRGD) for details.
- Enable three types of Zero Code Suppression when the ZCS[1:0]
(b1~0, T1/J1-TPLC-indirect registers - 01~18H) is configured.
- Enable the payload loopback by setting the LOOP (b2, T1/J1-
TPLC-indirect registers - 01~18H) (refer to Chapter 3.23.3 Payload
- Replace the data input from the TSDn/MTSD pin with the milliwatt
pattern when the DMW (b5, T1/J1-TPLC-indirect registers - 01~18H) is
logic 1. (The milliwatt is -law. Refer to Table 9.)
- Selected by the PRGDSEL[2:0] (b7~5, T1/J1-00FH), the test pat-
tern from the PRBS Generator/Detector will replace the data input from
the TSDn pin of one of the eight framers when the RXPATGEN (b2, T1/
J1-00FH) is ‘0’. The test pattern can replace the data in framed of
unframed mode, as determined by the UN_GEN (b1, T1/J1-00FH). In
unframed mode, all 24 channels and the F-bit are replaced and the per-
channel configuration in the TEST (b3, T1/J1-TPLC-indirect registers -
01~18H) is ignored. In framed mode, the received data will only be
replaced on the channel specified by the TEST (b3, T1/J1-TPLC-indirect
registers - 01~18H). Fractional T1/J1 signal will also be replaced in the
specified channel when the Nx56k_GEN (b4, T1/J1-00FH) is set. Refer
to Chapter 3.12 PRBS Generator / Detector (PRGD) for details.
- Replace the data input from the TSDn/MTSD pin with the value in
the IDLE[7:0] (b7~0, T1/J1-TPLC-indirect registers - 19~30H) when the
IDLE_DS0 (b6, T1/J1-TPLC-indirect registers - 01~18H) is set.
- Invert the most significant bit and/or the other bits in a channel
input from the TSDn pin when the SIGNINV and the INVERT (b4 & b7,
T1/J1-TPLC-indirect registers - 01~18H) are set.
(The above methods are arranged from highest to lowest in prior-
ity.)
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| IDT82V2108PXG8 | 功能描述:IC FRAMER T1/J1/E1 8CH 128-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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| IDT82V2604BB | 功能描述:IC INVERSE MUX 4CH ATM 208-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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| IDT82V2608 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:INVERSE MULTIPLEXING FOR ATM |
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