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參數(shù)資料
| 型號(hào)： | IDT82V3155PVG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 12/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL WAN T1/E1/OC3 DUAL 56SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，T1/E1/OC3 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CMOS，LVDS，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 32.768MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82V3155PVG8 |
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Description
2
February 20, 2009
IDT82V3155
ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
DESCRIPTION
The IDT82V3155 is an enhanced T1/E1/OC3 WAN PLL with dual
reference inputs. It contains a Digital Phase-Locked Loop (DPLL), which
generates low jitter ST-BUS, 19.44 MHz and 155.52 MHz clock and
framing signals that are phase locked to an 8 kHz, 1.544 MHz, 2.048
MHz or 19.44 MHz input reference.
The IDT82V3155 provides 10 types of clock signals (C1.5o, C3o,
C6o, C2o, C4o, C8o, C16o, C19o, C32o, C155) and 7 types of framing
signals (F0o, F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1
and STS3/OC3 links.
The IDT82V3155 is compliant with AT&T TR62411, Telcordia GR-
1244-CORE Stratum 3, Stratum 4 Enhanced, Stratum 4, OC-3 port,
155.52 Mbit/s application and ETSI ETS 300 011, ITU-T G.813 Option 1,
and ITU-T G.812 Type IV clocks. It meets the jitter/wander tolerance,
jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture
range, phase change slope, holdover frequency accuracy and MTIE
(Maximum Time Interval Error) requirements for these specifications.
The IDT82V3155 can be used in synchronization and timing control
for T1, E1 and OC3 systems, or used as ST-BUS clock and frame pulse
source. It also can be used in access switch, access routers, ATM edge
switches, wireless base station controllers, or IADs (Integrated Access
Devices), PBXs, line cards and SONET/SDH equipments.
PIN CONFIGURATION
Figure - 1 IDT82V3155 56-pin SSOP Package Pin Assignment
IDT82V3155
14
15
16
17
18
19
20
21
22
23
24
RST
MON_out0
Fref1
Fref0
F19o
OSCi
F8o
C1.5o
LOCK
C2o
C4o
FLOCK
F0_sel1
F0_sel0
C3o
C8o
C16o
C32o
F0o
F16o
1
2
3
4
5
6
7
8
9
10
11
12
13
56
55
54
RSP
TSP
C6o
VDDD
TDI
TMS
TRST
TDO
TCK
IC0
HOLDOVER
FREERUN
NORMAL
TIE_en
VDDD
VSS
C19o
MODE_sel0
MODE_sel1
TCLR
IN_sel
25
26
27
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
28
29
VDDD
VSS
VDDA
VSS
F32o
VSS
VDDA
C2/C1.5
IC2
F1_sel0
F1_sel1
C155NEG
C155POS
MON_out1
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| IDT82V3202 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL |
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| IDT82V32021NLBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL |
| IDT82V32021NLGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL |
| IDT82V3202EDGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL |
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