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參數(shù)資料
| 型號： | IDT82V3155PVG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 32/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL WAN T1/E1/OC3 DUAL 56SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，T1/E1/OC3 |
| 輸入： | 時鐘 |
| 輸出： | CMOS，LVDS，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 32.768MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82V3155PVG8 |
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Pin Description
7
February 20, 2009
IDT82V3155
ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
1
PIN DESCRIPTION
Name
Type
Pin Number
Description
VSS
Power
12, 18, 27
38, 47
Ground.
0 V. All VSS pins should be connected to the ground.
VDDA
Power
37, 48
3.3 V Analog Power Supply.
VDDD
Power
13, 19, 26
3.3 V Digital Power Supply.
OSCi
(CMOS) I
50
Oscillator Master Clock Input.
This pin is connected to a clock source.
Fref0
Fref1
I
5
6
Reference Input 0 and Reference Input 1.
These are two input reference sources (falling edge of 8 kHz, 1.544 MHz and 2.048 MHz or rising edge of 19.44
MHz) used for synchronization. The IN_sel pin determines which one of the two reference inputs to be used. See
Table - 4 for details.
The frequency of the reference inputs can be 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz. These two pins are
internally pulled up to VDDD.
IN_sel
I11
Input Reference Selection.
A logic low at this pin selects Reference Input 0 (Fref0) and a logic high at this pin selects Reference Input 1 (Fref1).
The logic level on this input is gated in by the rising edges of F8o. This Pin is internally pulled down to VSS.
F0_sel0
F0_sel1
I
9
10
Frequency Selection Inputs for Fref0.
These two inputs select one of the four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) for the
Reference Input 0 (Fref0). See Table - 2 for details.
F1_sel0
F1_sel1
I
35
34
Frequency Selection Inputs for Fref1.
These two inputs select one of the four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) for the
Reference Input 1 (Fref1). These two pins are internally pulled down to Vss. See Table - 3 for details.
MODE_sel0
MODE_sel1
I
1
2
Mode Selection Inputs.
These two inputs determine the operating mode of the IDT82V3155 (Normal, Holdover or Freerun). See Table - 1 for
details.
The logic levels on these two pins are gated in by the rising edges of F8o. These two pins are internally pulled down
to VSS.
RST
I4
Reset Input.
Pulling this pin to logic low for at least 300 ns will reset the IDT82V3155. While the RST pin is low, all framing and
clock outputs are at logic high.
To ensure proper operation, the device must be reset after it is powered up.
TCLR
I3
TIE Control Block Reset.
Pulling this pin to logic low for at least 300 ns will reset the TIE (Maximum Time Interval Error) control block and
result in a realignment of the output phase with the input phase. This pin is internally pulled up to VDDD.
TIE_en
I56
TIE Control Block Enable.
A logic high at this pin enables the TIE control block while a logic low disables it. The logic level on this input is gated
in by the rising edges of F8o. This pin is internally pulled down to Vss.
FLOCK
I45
Fast Lock Mode Enable.
When this pin is set to logic high, the DPLL will quickly lock to the input reference within 500 ms.
LOCK
(CMOS) O
44
Lock Indicator.
This output pin will go high when the DPLL is frequency locked to the input reference.
HOLDOVER
(CMOS) O
52
Holdover Indicator.
This output pin will go high whenever the DPLL enters Holdover mode.
NORMAL
(CMOS) O
46
Normal Indicator.
This output pin will go high whenever the DPLL enters Normal mode.
FREERUN
(CMOS) O
51
Freerun Indicator.
This output pin will go high whenever the DPLL enters Freerun mode.
MON_out0
O7
Frequency Out-of-range Indicator for Fref0.
A logic high at this pin indicates that Fref0 is off the nominal frequency by more than ±12 ppm.
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