Timing Characteristics
30
February 20, 2009
IDT82V3155
ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
tC8D
F8o to C8o delay
-2
0
+2
ns
tC16D
F8o to C16o delay
-2
0
+2
ns
tC19D
F8o to C19o delay
-8
0
+8
ns
tC32D
F8o to C32o delay
-2
2
+2
ns
tC155D
F8o to C155 delay
-3
0
+3
ns
tTSPD
F8o to TSP delay
-3
0
+3
ns
tRSPD
F8o to RSP delay
-3
0
+3
ns
t
C1.5o pulse width high or low
323
ns
tC3W
C3o pulse width high or low
161
ns
tC6W
C6o pulse width high or low
82
ns
tC2W
C2o pulse width high or low
244
ns
tC4W
C4o pulse width high or low
122
ns
tC8W
C8o pulse width high or low
61
ns
tC16W
C16o pulse width high or low
30.5
ns
tC19W
C19o pulse width high or low
25
ns
tC32WH
C32o pulse width high
14.4
ns
tC155W
C155 pulse width high or low
3.25
ns
tTSPW
TSP pulse width high
486
ns
tRSPW
RSP pulse width high
490
ns
tF0WL
F0o pulse width low
243
ns
tF8WH
F8o pulse width high
123.6
ns
tF16WL
F16o pulse width low
60.9
ns
tF19WH
F19o pulse width high
25
ns
t0RF
Output clock and frame pulse rise or fall time
3
ns
tS
Input controls setup Time
100
ns
tH
Input controls hold Time
100
ns
tF16D
F8o to F16o delay
27.1
30.1
33.1
ns
tF19D
F8o to F19o delay
17
25
33
ns
tF32D
F8o to F32o delay
12
15.8
19
ns
tF32S
F32o setup to C32o falling
11
ns
tF32H
F32o hold to C32o falling
11
ns
tF32WL
F32o pulse width low
30.6
ns
Parameter
Description
Min.
Typ.
Max.
Units
Test Conditions