參數(shù)資料
型號: IDT82V3155PVG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 5/34頁
文件大?。?/td> 0K
描述: IC PLL WAN T1/E1/OC3 DUAL 56SSOP
標(biāo)準(zhǔn)包裝: 1,000
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,T1/E1/OC3
輸入: 時鐘
輸出: CMOS,LVDS,TTL
電路數(shù): 1
比率 - 輸入:輸出: 2:12
差分 - 輸入:輸出: 無/是
頻率 - 最大: 32.768MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 56-SSOP
包裝: 帶卷 (TR)
其它名稱: 82V3155PVG8
Functional Description
13
February 20, 2009
IDT82V3155
ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
When the IDT82V3155 primarily enters the Holdover mode for a
short time period and then returns back to the Normal mode, the TIE
Control Circuit should not be enabled. This will prevent undesired
accumulated phase change between the input and output.
If the TIE Control Block is disabled manually or automatically, a
reference switch will result in a phase alignment between the input
signal and the output signal as shown in Figure - 6. The slope of the
phase adjustment is limited to 5 ns per 125 s.
Figure - 5 Reference Switch with TIE Control Block Enabled
Figure - 6 Reference Switch with TIE Control Block Disabled
Input Clock
Ref1
Ref2
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Output Clock
Input Clock
Ref1
Ref2
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Output Clock
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