參數(shù)資料
型號(hào)： IDT82V3155PVG8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 8/34頁(yè)
文件大?。?/td> 0K
描述： IC PLL WAN T1/E1/OC3 DUAL 56SSOP
標(biāo)準(zhǔn)包裝： 1,000
類型： 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，T1/E1/OC3
輸入： 時(shí)鐘
輸出： CMOS，LVDS，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 32.768MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 56-SSOP
包裝： 帶卷 (TR)
其它名稱： 82V3155PVG8
Functional Description
16
February 20, 2009
IDT82V3155
ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
2.8
OSC
The IDT82V3155 can use a clock as the master timing source. In the
Freerun mode, the frequency tolerance of the clock outputs is identical
to that of the source at the OSCi pin. For applications not requiring an
accurate Freerun mode, the tolerance of the master timing source may
be ±100 ppm. For applications requiring an accurate Freerun mode,
such as AT&T TR62411, the tolerance of the master timing source must
be no greater than ±32 ppm.
The desired capture range should be taken into consideration when
determining the accuracy of the master timing source. The sum of the
accuracy of the master timing source and the capture range of the
IDT82V3155 will always equal 230 ppm. For example, if the master
timing source is 100 ppm, the capture range will be 130 ppm.
2.8.1
CLOCK OSCILLATOR
When selecting a Clock Oscillator, numerous parameters must be
considered. This includes absolute frequency, frequency change over
temperature, output rise and fall times, output levels and duty cycle.
For applications requiring ±32 ppm clock accuracy, the following
clock oscillator module may be used.
FOX F7C-2E3-20.0 MHz
Frequency:
20.0 MHz
Tolerance:
25 ppm 0
°C to 70°C
Rise & Fall Time:10 ns (0.33 V, 2.97 V, 15 pF)
Duty Cycle:
40% to 60%
For Stratum 3 application, the clock oscillator should meet the
following requirements:
Frequency:
20.0 MHz
Tolerance:
±4.6 ppm over 20 years life time
Drift:
±0.04 ppm per day @ constant temperature
±0.3 ppm over temperature range of 0 to 70
°C
The output clock should be connected directly (not AC coupled) to
the OSCi input of the IDT82V3155, as shown in Figure - 8.
Figure - 8 Clock Oscillator Circuit
2.9
JTAG
The IDT82V3155 supports IEEE 1149.1 JTAG Scan.
2.10
RESET CIRCUIT
A simple power-up reset circuit is shown as Figure - 9. The logic low
reset pulse is about 50 s.
The resistor Rp is used for protection only and limits current into the
RST pin during power down conditions. The logic low reset pulse width
is not critical but should be greater than 300 ns.
Figure - 9 Power-Up Reset Circuit
+3.3 V
20 MHz OUT
GND
+3.3 V
OSCi
IDT82V3155
0.1
F
3.3 V
R
10 k
Rp
1 k
C
1
F
RST
IDT82V3155
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