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參數(shù)資料
| 型號： | IDT82V3155PVG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 21/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL WAN T1/E1/OC3 DUAL 56SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，T1/E1/OC3 |
| 輸入： | 時鐘 |
| 輸出： | CMOS，LVDS，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 32.768MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-SSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82V3155PVG8 |
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AC Electrical Characteristics
28
February 20, 2009
IDT82V3155
ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
7.14
19.44 MHZ INPUT JITTER TOLERANCE
Notes:
Voltages are with respect to ground (VSS) unless otherwise stated. Supply voltage and
operating temperature are as per Recommended Operating Conditions. Timing
parameters are as per Timing Parameter Measurement Voltage Levels.
1.
Fref0 reference input selected.
2.
Fref1 reference input selected.
3.
Normal mode selected.
4.
Holdover mode selected.
5.
Freerun mode selected.
6. 8 kHz frequency mode selected.
7.
1.544 MHz frequency mode selected.
8.
2.048 MHz frequency mode selected.
9. 19.44 MHz frequency mode selected.
10. Master clock input OSCi at 20 MHz ±0 ppm.
11.
Master clock input OSCi at 20 MHz ±32 ppm.
12. Master clock input OSCi at 20 MHz ±100 ppm.
13. Selected reference input at ±0 ppm.
14. Selected reference input at ±32 ppm.
15. Selected reference input at ±100 ppm.
16. For Freerun mode of ±0 ppm.
17. For Freerun mode of ±32 ppm.
18. For Freerun mode of ±100 ppm.
19. For capture range of ±230 ppm.
20. For capture range of ±198 ppm.
21. For capture range of ±130 ppm.
22. 25 pF capacitive load.
23. OSCi Master Clock jitter is less than 2 nspp, or 0.04 UIpp where 1 UIpp = 1/20 MHz.
24. Jitter on reference input is less than 7 nspp.
25. Applied jitter is sinusoidal.
26. Minimum applied input jitter magnitude to regain synchronization.
27. Loss of synchronization is obtained at slightly higher input jitter amplitudes.
28. Within 10 ms of the state, reference or input change.
29. 1 UIpp = 125 s for 8 kHz signals.
30. 1 UIpp = 648 ns for 1.544 MHz signals.
31. 1 UIpp = 488 ns for 2.048 MHz signals.
32. 1 UIpp = 323 ns for 3.088 MHz signals.
33. 1 UIpp = 244 ns for 4.096 MHz signals.
34. 1 UIpp = 158 ns for 6.312 MHz signals.
35. 1 UIpp = 122 ns for 8.192 MHz signals.
36. 1 UIpp = 61 ns for 16.484 MHz signals.
37. 1 UIpp = 51 ns for 19.44 MHz signals.
38. 1 UIpp = 30 ns for 32.968 MHz signals.
39. 1 UIpp = 6 ns for 155.52 MHz signals.
40. No filter.
41. 40 Hz to 100 kHz bandpass filter.
42. With respect to reference input signal frequency.
43. After a RST or TCLR.
44. Master clock duty 40% to 60%.
45. Prior to Holdover mode, device as in Normal mode and phase locked.
46. With input frequency offset of 100 ppm.
Description
Min.
Typ.
Max.
Units
Test Conditions / Notes
(see “Notes” on page 28)
Jitter tolerance for 12 Hz input
2800
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 178 Hz input
2800
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 0.0016 Hz input
311
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 0.0156 Hz input
311
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 0.125 Hz input
39
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 19.3 Hz input
39
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 500 Hz input
1.5
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 6.5 kHz input
1.5
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 65 kHz input
0.15
UIpp
1-3, 9-15, 22-23, 25-27, 37
Jitter tolerance for 1.3 MHz input
0.15
UIpp
1-3, 9-15, 22-23, 25-27, 37
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