參數(shù)資料
型號: IDT82V3155PVG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 22/34頁
文件大?。?/td> 0K
描述: IC PLL WAN T1/E1/OC3 DUAL 56SSOP
標準包裝: 1,000
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,T1/E1/OC3
輸入: 時鐘
輸出: CMOS,LVDS,TTL
電路數(shù): 1
比率 - 輸入:輸出: 2:12
差分 - 輸入:輸出: 無/是
頻率 - 最大: 32.768MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-BSSOP(0.295",7.50mm 寬)
供應商設備封裝: 56-SSOP
包裝: 帶卷 (TR)
其它名稱: 82V3155PVG8
Timing Characteristics
29
February 20, 2009
IDT82V3155
ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
8
TIMING CHARACTERISTICS
8.1
TIMING PARAMETER MEASUREMENT VOLTAGE LEVELS
Figure - 11 Timing Parameter Measurement Voltage Levels
Notes:
1. Voltages are with respect to ground (VSS) unless otherwise stated.
2. Supply voltage and operating temperature are as per Recommended Operating Conditions.
3. Timing for input and output signals is based on the worst case result of the CMOS thresholds.
8.2
INPUT/OUTPUT TIMING
Parameter
Description
CMOS
Units
VT
Threshold Voltage
0.5VDDD
V
VHM
Rise and Fall Threshold Voltage High
0.7VDDD
V
VLM
Rise and Fall Threshold Voltage Low
0.3VDDD
V
Parameter
Description
Min.
Typ.
Max.
Units
Test Conditions
tRW
Reference input pulse width high or low
51
ns
8 kHz, 1.544 MHz or 2.048 MHz
reference input
5
ns
19.44 MHz reference input
tIRF
Reference input rise or fall time
10
ns
tR8D
8 kHz reference input to F8o delay
8
ns
tR15D
1.544 MHz reference input to F8o delay
332
ns
tR2D
2.048 MHz reference input to F8o delay
253
ns
tR19D
19.44 MHz reference input to F8o delay
8
ns
tF0D
F8o to F0o delay
118
121
124
ns
tF16S
F16o setup to C16o falling
25
40
ns
tF16H
F16o hold to C16o falling
25
40
ns
tF19S
F19o setup to C19o falling
20
35
ns
tF19H
F19o hold to C19o falling
20
35
ns
tC15D
F8o to C1.5o delay
-3
0
+3
ns
tC3D
F8o to C3o delay
-3
1.6
+3
ns
tC6D
F8o to C6o delay
-3
1.6
+3
ns
tC2D
F8o to C2o
-2
0
+2
ns
tC4D
F8o to C4o
-2
0
+2
ns
Timing Reference Points
t
IRF,tORF
t
IRF,tORF
V
HM
V
T
V
LM
All Siganls
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