參數(shù)資料
型號： IDT82V3202NLG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 32/117頁
文件大?。?/td> 0K
描述： IC PLL WAN EBU SGL 68-VFQFPN
標準包裝： 2,500
類型： 時鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 68-VFQFPN（10x10）
包裝： 帶卷 (TR)
其它名稱： 82V3202NLG8
IDT82V3202
EBU WAN PLL
Functional Description
21
September 11, 2009
3.5
INPUT CLOCK QUALITY MONITORING
The qualities of the input clocks are always monitored in the following
aspects:
Activity
Frequency
The qualified clocks are available for T0 DPLL selection. The T0
selected input clock has to be monitored further. Refer to Chapter 3.7
3.5.1
ACTIVITY MONITORING
Activity is monitored by using an internal leaky bucket accumulator,
as shown in Figure 5.
Each input clock is assigned an internal leaky bucket accumulator.
The input clock is monitored for each period of 128 ms and the internal
leaky bucket accumulator increases by 1 when an event is detected; it
decreases by 1 if no event is detected within the period set by the decay
rate. The event is that an input clock drifts outside (>) ±500 ppm with
respect to the master clock within a 128 ms period.
There are four configurations (0 - 3) for a leaky bucket accumulator.
The leaky bucket configuration for an input clock is selected by the cor-
responding BUCKET_SEL[1:0] bits. Each leaky bucket configuration
consists of four elements: upper threshold, lower threshold, bucket size
and decay rate.
The bucket size is the capability of the accumulator. If the number of
the accumulated events reach the bucket size, the accumulator will stop
increasing even if further events are detected. The upper threshold is a
point above which a no-activity alarm is raised. The lower threshold is a
point below which the no-activity alarm is cleared. The decay rate is a
certain period during which the accumulator decreases by 1 if no event
is detected.
The leaky bucket configuration is programmed by one of four groups
of register bits: the BUCKET_SIZE_n_DATA[7:0] bits, the UPPER_
THRESHOLD_n_DATA[7:0] bits,
the LOWER_THRESHOLD_n_
DATA[7:0] bits and the DECAY_RATE_n_DATA[1:0] bits respectively; ‘n’
is 0 ~ 3.
The no-activity alarm status of the input clock is indicated by the
INn_CMOS_NO_ACTIVITY_ALARM bit (n = 1 or 2).
The input clock with a no-activity alarm is disqualified for clock selec-
tion for T0 DPLL.
Figure 5. Input Clock Activity Monitoring
Input Clock
Leaky Bucket Accumulator
No-activity Alarm Indication
Decay
Rate
Bucket Size
Upper Threshold
Lower Threshold
0
clock signal with no event
clock signal with events
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82V3202NLGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL
IDT82V3255 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255_08 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255DK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255DKG 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
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