參數(shù)資料
型號： IDT82V3202NLG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 46/117頁
文件大?。?/td> 0K
描述： IC PLL WAN EBU SGL 68-VFQFPN
標(biāo)準(zhǔn)包裝： 2,500
類型： 時鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 68-VFQFPN（10x10）
包裝： 帶卷 (TR)
其它名稱： 82V3202NLG8
IDT82V3202
EBU WAN PLL
Functional Description
34
September 11, 2009
3.11
DPLL OUTPUT
The DPLL output is locked to the selected input clock. According to
the phase-compared result of the feedback and the selected input clock,
and the DPLL output frequency offset, the PFD output is limited and the
DPLL output is frequency offset limited.
3.11.1
PFD OUTPUT LIMIT
The PFD output is limited to be within ±1 UI or within the coarse
phase limit (refer to Chapter 3.7.1.2 Coarse Phase Loss), as determined
by the MULTI_PH_APP bit.
3.11.2
FREQUENCY OFFSET LIMIT
The DPLL output is limited to be within the DPLL hard limit (refer to
The integral path value can be frozen when the DPLL hard limit is
reached. This function, enabled by the T0_LIMT bit, will minimize the
subsequent overshoot when T0 DPLL is pulling in.
3.11.3
PBO
When a PBO event is triggered, the phase offset of the selected input
clock with respect to the T0 DPLL output is measured. The device then
automatically accounts for the measured phase offset and compensates
an appropriate phase offset into the DPLL output so that the phase tran-
sients on the T0 DPLL output are minimized.
A PBO event is triggered if any one of the following conditions
occurs:
T0 selected input clock switches (the PBO_EN bit is ‘1’);
T0 DPLL exits from Holdover mode or Free-Run mode (the
PBO_EN bit is ‘1’);
Phase-time changes on the T0 selected input clock are greater
than a programmable limit over an interval of less than 0.1 sec-
onds (the PH_MON_PBO_EN bit is ‘1’).
For the first two conditions, the phase transients on the T0 DPLL out-
put are minimized to be no more than 0.61 ns with PBO. The PBO can
also be frozen at the current phase offset by setting the PBO_FREZ bit.
When the PBO is frozen, the device will ignore any further PBO events
triggered by the above two conditions, and maintain the current phase
offset. When the PBO is disabled, there may be a phase shift on the T0
DPLL output and the T0 DPLL output tracks back to 0 degree phase off-
set with respect to the T0 selected input clock.
The last condition is specially for stratum 2 and 3E clocks. The PBO
requirement specified in the Telcordia GR-1244-CORE is: ‘Input phase-
time changes of 3.5 s or greater over an interval of less than 0.1 sec-
onds or less shall be built-out by stratum 2 and 3E clocks to reduce the
resulting clock phase-time change to less than 50 ns. Phase-time
changes of 1.0 s or less over an interval of 0.1 seconds shall not be
built-out.’ Based on this requirement, phase-time changes of more than
1.0 s but less than 3.5 s that occur over an interval of less than 0.1
seconds may or may not be built-out.
An integrated Phase Transient Monitor can be enabled by the
PH_MON_EN bit to monitor the phase-time changes on the T0 selected
input clock. When the phase-time changes are greater than a limit over
an interval of less than 0.1 seconds, a PBO event is triggered and the
phase transients on the DPLL output are absorbed. The limit is pro-
grammed by the PH_TR_MON_LIMT[3:0] bits, and can be calculated as
follows:
Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156
The phase offset induced by PBO will never result in a coarse or fine
phase loss.
3.11.4
FOUR PATHS OF T0 DPLL OUTPUTS
The T0 DPLL output are phase aligned with the T0 selected input
clock every 125 s period. T0 DPLL has four output paths as follows:
77.76 MHz path - outputs a 77.76 MHz clock;
16E1/16T1 path - outputs a 16E1 or 16T1 clock, as selected by
the IN_SONET_SDH bit;
GSM/OBSAI/16E1/16T1 path - outputs a GSM, OBSAI, 16E1 or
16T1 clock, as selected by the T0_GSM_OBSAI_16E1_16T1_
SEL[1:0] bits;
12E1/24T1/E3/T3 path - outputs a 12E1, 24T1, E3 or T3 clock,
as selected by the T0_12E1_24T1_E3_T3_SEL[1:0] bits.
T0 selected input clock is compared with a T0 DPLL output for DPLL
locking. The output can only be derived from the 77.76 MHz path or the
16E1/16T1 path. The output path is automatically selected and the out-
put is automatically divided to get the same frequency as the T0
selected input clock.
T0 DPLL outputs are provided for T0/T4 APLL or device output pro-
cess.
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