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參數(shù)資料
| 型號： | IDT82V3202NLG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 50/117頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL WAN EBU SGL 68-VFQFPN |
| 標準包裝： | 2,500 |
| 類型： | 時鐘/頻率發(fā)生器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS |
| 輸出： | CMOS，LVDS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應商設(shè)備封裝： | 68-VFQFPN（10x10） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82V3202NLG8 |
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IDT82V3202
EBU WAN PLL
Functional Description
38
September 11, 2009
3.13.2
FRAME SYNC OUTPUT SIGNAL
An 8 kHz frame sync signal is output on the FRSYNC_8K pin if
enabled by the 8K_EN bit. It is a CMOS output.
The frame sync signal is derived from the T0 APLL output and are
aligned with the output clock. It can be synchronized to one of the two
frame sync input signals.
One of the two frame sync input signals is selected, as determined
by the SYNC_BYPASS bit and the T0 selected input clock, as shown in
If the selected frame sync input signal with respect to the T0 selected
input clock is above a limit set by the SYNC_MON_LIMT[2:0] bits, an
external sync alarm will be raised and the selected frame sync input sig-
nal is disabled to synchronize the frame sync output signal. The external
sync alarm is cleared once the selected frame sync input signal with
respect to the T0 selected input clock is within the limit. If it is within the
limit, whether the selected frame sync input signal is enabled to synchro-
nize the frame sync output signal is determined by the SYNC_BYPASS
bit, the AUTO_EXT_SYNC_EN bit and the EXT_SYNC_EN bit. Refer to
Table 25 for details.
When the selected frame sync input signal is enabled to synchronize
the frame sync output signal, it should be adjusted to align itself with the
T0 selected input clock. Nominally, the falling edge of the selected frame
sync input signal is aligned with the rising edge of the T0 selected input
clock. The selected frame sync input signal may be 0.5 UI early/late or 1
UI late due to the circuit and board wiring delays. Setting the sampling of
the selected frame sync input signal by the SYNC_PHn[1:0] bits (n = 1
or 2 corresponding to EX_SYNC1 or EX_SYNC2 respectively) will com-
The EX_SYNC_ALARM_MON bit indicates whether the selected
frame sync input signal is in external sync alarm status. The external
sync alarm is indicated by the EX_SYNC_ALARM 1 bit. If the
EX_SYNC_ALARM 2 bit is ‘1’, the occurrence of the external sync alarm
will trigger an interrupt.
The 8 kHz frame sync output signal can be inverted by setting the
8K_INV bit. The frame sync output can be 50:50 duty cycle or pulsed, as
determined by the 8K_PUL bit. When they are pulsed, the pulse width is
defined by the period of OUT2; and they are pulsed on the position of
the falling or rising edge of the standard 50:50 duty cycle, as selected by
the 8K_PUL_POSITION bit.
Figure 8. On Target Frame Sync Input Signal Timing
Figure 9. 0.5 UI Early Frame Sync Input Signal Timing
Table 24: Frame Sync Input Signal Selection
SYNC_BYPASS T0 Selected Input Clock
Selected Frame Sync Input
Signal
0
don’t-care
EX_SYNC1
1
IN1_CMOS
EX_SYNC1
IN2_CMOS
EX_SYNC2
none
Table 25: Synchronization Control
SYNC_BYPASS
AUTO_EXT_SYNC_EN
EXT_SYNC_EN
Synchronization
0
don’t-care
0
Disabled
01
Enabled
1
Disabled
1
don’t-care
Enabled
T0 selected
input clock
Output clocks
Selected frame
sync input signal
Frame sync
output signals
T0 selected
input clock
Output clocks
Selected frame
sync input signal
Frame sync
output signals
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3202NLGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL |
| IDT82V3255 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255_08 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255DK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255DKG | 功能描述:IC PLL WAN SMC STRATUM 3 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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