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| 型號： | intel Pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor Mobile Module(帶移動模塊奔II處理器) |
| 中文描述： | 奔騰II處理器的移動模塊（帶移動模塊奔二處理器） |
| 文件頁數(shù)： | 11/46頁 |
| 文件大?。?/td> | 681K |
| 代理商： | INTEL PENTIUM II PROCESSOR |
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11
INTEL
PENTIUM
II PROCESSOR MOBILE MODULE MMC-1
Name
Type
Voltage
Description
PCI_RST#
I
CMOS
V_3
Reset:
When asserted, this signal asynchronously resets the
443BX Host Bridge.
The PCI signals also tri-state, compliant with
PCI Rev 2.1 specifications.
3.1.4
Processor and PIIX4E Sideband (9
Signals)
Table 4 lists the processor and PIIX4E sideband interface
signals. These voltage levels are determined by V_CPUIO.
Table 4. Processor/PIIX4E Sideband Signal Descriptions
Type
Voltage
Description
Name
FERR#
O
CMOS
V_CPUIO
Numeric Coprocessor Error:
This pin functions as a FERR#
signal supporting coprocessor errors. This signal is tied to the
coprocessor error signal on the processor and is driven by the
processor to the PIIX4E.
CPURST
N/C
CMOS
ID
CMOS
ID
CMOS
ID
CMOS
V_CPUIO
Processor Reset:
The signal is not used in the Pentium
II
Processor MMC-1.
IGNNE#
V_CPUIO
Ignore Error:
This open drain signal is connected to the ignore
error pin on the processor and is driven by the PIIX4E.
INIT#
V_CPUIO
Initialization:
INIT# is asserted by the PIIX4E to the processor for
system initialization. This signal is an open drain.
INTR
V_CPUIO
Processor Interrupt:
INTR is driven by the PIIX4E to signal the
processor that an interrupt request is pending and needs to be
serviced. This signal is an open drain.
NMI
ID
CMOS
V_CPUIO
Non-Maskable Interrupt:
NMI is used to force a non-maskable
interrupt to the processor.
The PIIX4E ISA bridge generates an
NMI when either SERR# or IOCHK# is asserted, depending on
how the NMI Status and Control Register is programmed. This
signal is an open drain.
A20M#
ID
CMOS
V_CPUIO
Address Bit 20 Mask:
When enabled, this open drain signal
causes the processor to emulate the address wraparound at one
MB which occurs on the Intel 8086 processor.
SMI#
ID
CMOS
V_CPUIO
System Management Interrupt:
SMI# is an active low
synchronous output from the PIIX4E that is asserted in response
to one of many enabled hardware or software events.
The SMI#
open drain signal can be an asynchronous input to the processor.
However, in this chip set SMI# is synchronous to PCLK.
STPCLK#
ID
CMOS
V_CPUIO
Stop Clock:
STPCLK# is an active low synchronous open drain
output from the PIIX4E that is asserted in response to one of
many hardware or software events.
STPCLK# connects directly to
the processor and is synchronous to PCICLK.
When the
processor samples STPCLK# asserted it responds by entering a
low power state (Quick Start). The processor will only exit this
mode when this signal is deasserted.
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