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參數(shù)資料
| 型號(hào)： | intel Pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor Mobile Module(帶移動(dòng)模塊奔II處理器) |
| 中文描述： | 奔騰II處理器的移動(dòng)模塊（帶移動(dòng)模塊奔二處理器） |
| 文件頁數(shù)： | 19/46頁 |
| 文件大?。?/td> | 681K |
| 代理商： | INTEL PENTIUM II PROCESSOR |
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19
INTEL
PENTIUM
II PROCESSOR MOBILE MODULE MMC-1
Table 11 summarizes the key specifications for the MMC-1.
Table 11. Connector Specifications
Condition
Parameter
Specification
Material
Contact
Copper Alloy
Housing
Thermo Plastic Molded Compound: LCP
Electrical
Current
0.5 A
Voltage
50 VAC
Insulation Resistance
100 M
min. at 500 VDC
Termination Resistance
20 m
max. at 20 mV open circuit with 10 mA
Capacitance
5 pF max. per contact
Mechanical
Mating Cycles
50 cycles
Connector Mating Force
0.9N (90 gf) max. per contact
Contact Un-mating Force
0.1N (10gf) min. per contact
4.0.
FUNCTIONAL DESCRIPTION
4.1.
Pentium
II Processor Mobile Module
The Pentium
II processor mobile module supports the
Mobile Pentium II processor core with 32 KB L1 data cache,
the 443BX Host Bridge System Controller, and system level
support. The mobile Pentium II processor includes a 66-MHz
system bus speed and offers speeds of 300 MHz, 266 MHz,
and 233 MHz.
4.2.
L2 Cache
The Mobile Pentium
II processor core’s internal cache is
enhanced by a second-level cache using a high-
performance pipeline burst SRAM. SRAM uses a dedicated
high-speed bus into the processor core. The L2 cache can
support 512 MB of system memory. The maximum amount
of cacheable system memory supported by the 443BX Host
Bridge system controller is 256 MB with 16-Mbit DRAMs.
(The system controller can support up to 1 GB of system
memory using 64-Mbit technology.) The Pentium II processor
mobile module has two 100-pin TQFP footprints for 512K
direct-mapped write-back L2 cache.
The Pentium II processor mobile module supports the “Stop
Clock” mode of power management for the L2 SRAMs. In
this mode, the clock signals to the synchronous SRAMs are
“parked” in a low power state.
4.3.
The 443BX Host Bridge System
Controller
Intel’s
443BX Host Bridge system controller combines the
mobile Pentium
II processor bus controller, the DRAM
controller, and the PCI bus controller. The 443BX Host
Bridge has multiple power management features designed
specifically for notebook systems such as:
CLKRUN#, a feature that enables controlling of the PCI
clock on or off.
The 443BX Host Bridge suspend modes, including
Suspend-to-RAM (STR), Suspend-to-Disk (STD), and
Powered-On-Suspend (POS).
System Management RAM (SMRAM) power
management modes, including Compatible SMRAM
(C_SMRAM) and Extended SMRAM (E_SMRAM).
C_SMRAM is the traditional SMRAM feature
implemented in all Intel PCI chipsets. E_SMRAM is a
new feature that supports write-back cacheable
SMRAM space up to 1 MB. To minimize power
consumption while the system is idle, the internal
443BX Host Bridge clock is turned off (gated off). This
is accomplished by setting the G_CLK enable bit in the
power management register in the 443BX through the
system BIOS.
Pentium II processor mobile modules support only the
443BX Host Bridge features in mobile compatible mode.
Refer to Intel’s latest revision of the 443BX Host Bridge
specification for complete details.
4.3.1.
Memory Organization
The memory interface of the 443BX Host Bridge is available
at the MMC-1 allowing support for the following:
One set of memory control signals sufficient to support
up to three SO_DIMM sockets and six banks of
SDRAM at 66 MHz.
One CKE signal for all banks.
Memory features not supported by the MMC-1 are:
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