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| 型號(hào)： | intel Pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor Mobile Module(帶移動(dòng)模塊奔II處理器) |
| 中文描述： | 奔騰II處理器的移動(dòng)模塊（帶移動(dòng)模塊奔二處理器） |
| 文件頁數(shù)： | 26/46頁 |
| 文件大小： | 681K |
| 代理商： | INTEL PENTIUM II PROCESSOR |
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26
INTEL
PENTIUM
II PROCESSOR MOBILE MODULE MMC-1
4.6.2
AC Requirements
Table 16 provides the BCLK AC requirements.
Table 16. Pentium
II Processor Mobile Module AC Specifications (BCLK)
at the Processor Core Pins
1, 2, 3
Parameter
Min
T#
Nom
Max
Unit
Figure
Notes
System Bus Frequency
66.67
MHz
All processor core
frequencies
4
T1:
BCLK Period
15.0
ns
4, 5
T2:
BCLK Period Stability
±250
ps
6, 7, 8
T3:
BCLK High Time
5.3
ns
At >1.8V
T4:
BCLK Low Time
5.3
ns
At <0.7V
T5:
BCLK Rise Time
0.175
0.875
ns
(0.9V-1.6V)
8
T6:
BCLK Fall Time
0.175
0.875
ns
(1.6V–0.9V)
8
NOTES:
1.
2.
Unless otherwise noted, all specifications in this table apply to all Intel mobile modules.
All AC timings for the GTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor core pin. All GTL+ signal
timings (address bus, data bus, etc.) are referenced at 1.00V at the processor core pins.
All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25V at the processor core pin. All CMOS signal
timings (compatibility signals, etc.) are referenced at 1.25V at the processor core pins.
The internal core clock frequency is derived from the system bus clock. The system bus clock to core clock ratio is determined during
initialization as described and is predetermined by the Pentium II processor mobile module.
The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the CK97 Clock Synthesizer/Driver Specificationfor further
information.
Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a component of BCLK skew
between devices.
The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the jitter created by the clock
driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should be less than500 kHz. This specification may be
ensured by design characterization and/or measured with a spectrum analyzer. See the
CK97 Clock Synthesizer/Driver Specification
for further details.
Not 100% tested. Specified by design characterization as a clock driver requirement.
3.
4.
5.
6.
7.
8.
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