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| 型號： | intel Pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | Pentium II Processor Mobile Module(帶移動模塊奔II處理器) |
| 中文描述： | 奔騰II處理器的移動模塊（帶移動模塊奔二處理器） |
| 文件頁數(shù)： | 27/46頁 |
| 文件大?。?/td> | 681K |
| 代理商： | INTEL PENTIUM II PROCESSOR |
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27
INTEL
PENTIUM
II PROCESSOR MOBILE MODULE MMC-1
4.6.2.1.
System Bus Clock (BCLK) Signal Quality
Specifications and Measurement
Guidelines
Table 17 describes the signal quality specifications at the
processor core for the BCLK signal.
Figure 4 describes the signal quality waveform for the BCLK
at the processor core pins.
Table 17. BCLK Signal Quality Specifications at the Processor Core
Min
Nom
T#
Parameter
Max
Unit
Figure
Notes
V1:
BCLK V
IL
0.7
V
4
2
V2:
BCLK V
IH
V
IN
Absolute Voltage Range
Rising Edge Ringback
1.8
V
4
2
V3:
–0.8
3.5
V
4
3
V4:
1.8
V
4
4
V5:
Falling Edge Ringback
0.7
V
4
4
BCLK rising/falling slew rate
0.8
4
V/ns
NOTES:
1.
2.
3.
4.
Unless otherwise noted, all specifications in this table apply to all Intel mobile modules.
BCLK must rise/fall monotonically between V
IL,BCLK
and V
IH, BCLK.
The system bus clock overshoot and undershoot specification for the 66-MHz system bus operation.
The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal
can dip back to after passing the V
IH
(rising) or V
IL
(falling) voltage limits.
For proper signal termination, refer to the Clocking Guidelines in the Mobile Pentium
II Processor / 440BX PCIset Advanced
Platform Recommend Design and Debug Practices.
5.
V2
V1
V3
V3
T3
V5
V4
T6
T4
T5
000806
Figure 4. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pin
4.7.
Voltage Regulator
The DC voltage regulator (DC/DC converter) provides the
appropriate core voltage, the I/O ring voltage, and the
sideband signal pullup voltage. The voltage range is 5V –
21V.
4.7.1.
Voltage Regulator Efficiency
Table 18 lists the voltage regulator efficiencies.
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