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參數資料
| 型號： | INTEL486 GX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 GX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486 GX處理器（嵌入式超低能量處理器） |
| 文件頁數： | 11/48頁 |
| 文件大小： | 409K |
| 代理商： | INTEL486 GX |
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Embedded Ultra-Low Power Intel486 GX Processor
7
3.2
Pin Quick Reference
The following is a brief pin description. For detailed signal descriptions refer to Appendix A, “Signal Descrip-
tions,” in the Embedded Intel486 Processor Family Developer’s Manual,
order No. 273021.
Table 4. Embedded ULP Intel486
GX Processor Pin Descriptions
(Sheet 1 of 6)
Symbol
CLK
Type
I
Name and Function
Clock
provides the fundamental timing and internal operating frequency for the
embedded ULP Intel486 GX processor. All external timing parameters are
specified with respect to the rising edge of CLK.
ADDRESS BUS
A31-A4
A3–A2
I/O
O
Address Lines
A31–A2, together with the byte enable signals, BE3#–BE0#,
define the physical area of memory or input/output space accessed. Address lines
A31–A4 are used to drive addresses into the embedded ULP Intel486 GX
processor to perform cache line invalidation. Input signals must meet setup and
hold times t
22
and t
23
. A31–A2 are not driven during bus or address hold.
Byte Enable
signals indicate active bytes during read and write cycles. During the
first cycle of a cache fill, the external system should assume that all byte enables
are active. BE3#–BE0# are active LOW and are not driven during bus hold.
BE3# applies to processor data bits D31–D24
BE2# applies to processor data bits D23–D16
BE1# applies to processor data bits D15–D8
BE0# applies to processor data bits D7–D0
The byte enables can be used by the external system to generate address bits A1
and A0, as well as byte-high (D15-D8) and byte-low (D7-D0) enables. These are
needed to interpret the 16-bit external data bus.
BE3#
BE2#
BE1#
BE0#
O
O
O
O
DATA BUS
D15
–D0
I/O
Data Lines.
D7–D0 define the least significant byte of the data bus; D15-D8 define
the most significant byte of the data bus. These signals must meet setup and hold
times t
and t
for proper operation on reads. These pins are driven during the
second and subsequent clocks of write cycles.
There is one
Data Parity
pin for each byte of the data bus. Data parity is generated
on all write data cycles with the same timing as the data driven by the embedded
ULP Intel486 GX processor. Even parity information must be driven back into the
processor on the data parity pins with the same timing as read information to
ensure that the correct parity check status is indicated by the processor. The
signals read on these pins do not affect program execution.
Input signals must meet setup and hold times t
22
and t
23
. DP1 and DP0 must be
connected to V
CCP
through a pull-up resistor in systems that do not use parity. DP1
and DP0 are active HIGH and are driven during the second and subsequent clocks
of write cycles.
DP1
DP0
I/O
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